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SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded
Product List
SM59R16A2L25, SM59R16A2C25 SM59R08A2L25, SM59R08A2C25
Features
Operating Voltage: 4.5V ~ 5.5V or 2.7V ~ 3.6V High speed architecture of 1 clock/machine cycle (1T), runs up to 25MHz 1T/2T can be switched on the fly Instruction-set compatible with MCS-51 Internal OSC with range 1MHz - 24MHz 64K/32K bytes on-chip program memory
Description
The SM59R16A2/SM59R08A2 is a 1T (one machine cycle per clock) single-chip 8-bit microcontroller. It has 64K/32K-byte embedded Flash for program, and executes all ASM51 instructions fully compatible with MCS-51. SM59R16A2/SM59R08A2 contains 2KB on-chip RAM, 48 GPIOs, various serial interfaces and many peripheral functions as described below. It can be programmed via writers. Its on-chip ICE is convenient for users in verification during development stage. The high performance of SM59R16A2/ SM59R08A2 can achieve complicated manipulation within short time. About one third of the instructions are pure 1T, and the average speed is 8 times of traditional 8051, the fastest one among all the 1T 51-series. Its excellent EMI and ESD characteristics are advantageous for many different applications.
External RAM addresses up to 64K bytes.
Standard 12T interface for external RAM access.
256 bytes RAM as standard 8052, plus 2K bytes on-chip expandable RAM Dual 16-bit Data Pointers (DPTR0 & DPTR1) Two serial peripheral interfaces in full duplex mode (UART0 & UART1), Three 16-bit Timers/Counters. (Timer 0 , 1, 2) 48 GPIOs External interrupt 0,1 with two priority levels Programmable watchdog timer (WDT) One IIC interface (Master/Slave mode) One SPI interface (Master/Slave mode) 4-channel PWM (12-bit, 10-bit, 8-bit options) 4-channel 16-bit compare /capture /load functions 4-channel 10-bit analog-to-digital converter (ADC)
Ordering Information
SM59R16A2(SM59R08A2)ihhkL yymmv i: process identifier {L = 2.7V ~ 3.6V, C = 4.5V ~ 5.5V} hh: working clock in MHz {25} k: package type postfix {as table below } L:PB Free identifier {No text is Non-PB free"P" is PB free} yy: year mm: month v: version identifier{ A, B,...}
Postfix W U Package 64L TQFP 64L LQFP Pin / Pad Configuration Page 2,3 Page 2,3
ISP/ IAP functions.
EEPROM function On-chip in-circuit emulator (ICE) function with On-Chip DebuggerOCD Fast multiplication-division unit (MDU) : 16*16, 32/16, 16/16, 32-bit L/R shifting and 32-bit normalization Expanded External Interrupt (EEI) interface on Port 1 for eight more interrupts Enhanced user code protection Power management unit for idle and power down modes
Contact SyncMOS : www.syncmos.com.tw 6F, No.10-2 Li- Hsin 1st Road , SBIP, Hsinchu, Taiwan TEL: 886-3-567-1820 FAX: 886-3-567-1891
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 1 Ver.B SM59R16A2/SM59R08A2 06/2009
SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded
Pin Configuration
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 2 Ver.B SM59R16A2/SM59R08A2 06/2009
SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 3 Ver.B SM59R16A2/SM59R08A2 06/2009
SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded
Block Diagram
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 4 Ver.B SM59R16A2/SM59R08A2 06/2009
SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded
Pin Description
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Name P5.2 P5.3 P5.4 P5.5 P5.6 P5.7 VDDIO VSSIO P4.0/PWM2 P4.1/PWM3 P4.2 P4.3 P4.4/ADC0 P4.5/ADC1 P4.6/ADC2 P4.7/ADC3 XTAL1 XTAL2 NC P1.7/IIC_SDA P1.6/IIC_SCL P1.5/PWM1/CC1 P1.4/PWM0/CC0 AVDD AVDD3V AVSS P1.3/TXD1/CC3/SPI_MOSI i/o I/O i/o i/o i/o i/o i/o i/o Description Bit 2 of port 5 Bit 3 of port 5 Bit 4 of port 5 Bit 5 of port 5 Bit 6 of port 5 Bit 7 of port 5 Power supply Digital ground Bit 0 of port 4 & PWM Channel 2 Bit 1 of port 4 & PWM Channel 3 Bit 2 of port 4 Bit 3 of port 4 Bit 4 of port 4 & ADC channel 0 Bit 5 of port 4 & ADC channel 1 Bit 6 of port 4 & ADC channel 2 Bit 7 of port 4 & ADC channel 3 Crystal input Crystal output No Connect Bit 7 of port 1 & IIC SDA pin Bit 6 of port 1 & IIC SCL pin Bit 5 of port 1 & PWM Channel 1 & Timer 2 compare/capture Channel 1 Bit 4 of port 1 & PWM Channel 0 & Timer 2 compare/capture Channel 0 Analog Power supply Analog Power supply Analog ground Bit 3 of port 1 & Serial interface channel 1 & Timer 2 compare/capture Channel 3 & SPI interface Serial Data Input pin Bit 2 of port 1 & Serial interface channel 1 & Timer 2 compare/capture Channel 2 & SPI interface Serial Data Out pin Bit 1 of port 1 & Timer 2 capture trigger & SPI interface Clock pin Bit 0 of port 1 & Timer 2 external input clock & SPI interface Slave Select pin Bit 7 of port 2 & Bit 15 of external memory address Bit 6 of port 2 & Bit 14 of external memory address Bit 5 of port 2 & Bit 13 of external memory address Bit 4 of port 2 & Bit 12 of external memory address Bit 3 of port 2 & Bit 11 of external memory address Bit 2 of port 2 & Bit 10 of external memory address Bit 1 of port 2 & Bit 9 of external memory address Bit 0 of port 2 & Bit 8 of external memory address Bit 7 of port 3 & external memory read signal Bit 6 of port 3 & external memory write signal
i/o i/o i/o i/o i/o i/o i/o i/o i o i i/o i/o i/o i/o
28 29 30 31 32 33 34 35 36 37 38 39 40
P1.2/RXD1/CC2/SPI_MISO P1.1/T2EX/SPI_CLK P1.0/T2/SPI_SS P2.7/A15 P2.6/A14 P2.5/A13 P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9 P2.0/A8 P3.7/RD P3.6/WR
i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 5 Ver.B SM59R16A2/SM59R08A2 06/2009
SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded Pin 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Name P3.5/T1 P3.4/T0 P3.3/INT1 P3.2/INT0 P3.1/TXD0 P3.0/RXD0 P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VSS VDD3V VDD ICE_ICP_BUSY ICE_ICP_DATA ICE_ICP_CLOCK ALE RESET P5.0 P5.1 I/O i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o Description Bit 5 of port 3 & Timer 1 external input Bit 4 of port 3 & Timer 0 external input Bit 3 of port 3 & External interrupt 1 Bit 2 of port 3 & External interrupt 0 Bit 1 of port 3 & Serial interface channel 0 Bit 0 of port 3 & Serial interface channel 0 Bit 7 of port 0 & Bit 7 of external memory address/data Bit 6 of port 0 & Bit 6 of external memory address/data Bit 5 of port 0 & Bit 5 of external memory address/data Bit 4 of port 0 & Bit 4 of external memory address/data Bit 3 of port 0 & Bit 3 of external memory address/data Bit 2 of port 0 & Bit 2 of external memory address/data Bit 1 of port 0 & Bit 1 of external memory address/data Bit 0 of port 0 & Bit 0 of external memory address/data Digital ground Digital Power supply Digital Power supply Busy (active low during Flash programming) signal in ICE or ICP functions Command and data IO synchronous to ICE_ICP_CLOCK in ICE or ICP functions Clock input of ICE and ICP functions
o i/o i o i i/o i/o
Address latch enable
Reset pin Bit 0 of port 5 Bit 1 of port 5
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 6 Ver.B SM59R16A2/SM59R08A2 06/2009
SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded
Special Function Register (SFR)
A map of the Special Function Registers is shown as below:
Hex\Bin F8 F0 E8 E0 D8 D0 C8 C0 B8 B0 A8 A0 98 90 88 80 X000 IICS B P4 ACC BRGS PSW T2CON IRCON IEN1 P3 IEN0 P2 S0CON P1 TCON P0 X001 IICCTL SPIC1 MD0 X010 IICA1 SPIC2 MD1 X011 IICA2 SPITXD MD2 X100 IICRWD SPIRXD MD3 X101 SPIS MD4 X110 X111 Bin/Hex FF F7 EF E7 DF D7 CF C7 BF B7 AF A7 9F 97 8F 87
MD5
ARCON
CCEN IP1 PWMD2H IP0 PES S0BUF P5 TMOD SP
CRCL CCL1 S0RELH PWMD2L S0RELL IEN2 DPS TL0 DPL
CRCH CCH1 S1RELH PWMD3H ADCC1 S1CON KBLS TL1 DPH
TL2 CCL2 PWMD0H PWMD3L ADCC2 S1BUF KBE TH0 DPL1
TH2 CCH2 PWMD0L PWMC ADCDH S1RELL KBF TH1 DPH1
CCL3 PWMD1H WDTC ADCDL
CCH3 PWMD1L WDTK CLKR
IFCON PCON
Note: Special Function Registers reset values and description for SM59R16A2/SM59R08A2
Register P0 SP DPL DPH DPL1 DPH1 PCON TCON TMOD TL0 TL1 TH0 TH1 IFCON P1 P5 DPS KBLS KBE Location 80h 81h 82h 83h 84h 85h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Fh 90h 91h 92h 93h 94h Reset value FFh 07h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h FFh FFh 00h 00h 00h Port 0 Stack Pointer Data Pointer 0 low byte Data Pointer 0 high byte Data Pointer 1 low byte Data Pointer 1 high byte Power Control Timer/Counter Control Timer Mode Control Timer 0, low byte Timer 1, low byte Timer 0, high byte Timer 1, high byte Interface control register Port 1 Port 5 Data Pointer select Register Expanded External Interrupt (EEI) level selector register Expanded External Interrupt (EEI) input enable register Description
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 7 Ver.B SM59R16A2/SM59R08A2 06/2009
SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded Register KBF S0CON S0BUF IEN2 S1CON S1BUF S1RELL P2 PES IEN0 IP0 S0RELL ADCC1 ADCC2 ADCDH ADCDL CLKR P3 PWMD2H PWMD2L PWMD3H PWMD3L PWMC WDTC WDTK IEN1 IP1 S0RELH S1RELH PWMD0H PWMD0L PWMD1H PWMD1L IRCON CCEN CCL1 CCH1 CCL2 Location 95h 98h 99h 9Ah 9Bh 9Ch 9Dh A0h A1h A8h A9h AAh ABh ACh ADh AEh AFh B0h B1h B2h B3h B4h B5h B6h B7h B8h B9h BAh BBh BCh BDh BEh BFh C0h C1h C2h C3h C4h Reset value 00h 00h 00h 00h 00h 00h 00h FFh 00h 00h 00h D9h 00h 00h 00h 00h 03h FFh 00h 00h 00h 00h 00h 00h 00h 00h 00h 03h 03h 00h 00h 00h 00h 00h 00h 00h 00h 00h Description Expanded External Interrupt (EEI) interrupt flag register Serial Port 0, Control Register Serial Port 0, Data Buffer Interrupt Enable Register 2 Serial Port 1, Control Register Serial Port 1, Data Buffer Serial Port 1, Reload Register, low byte Port 2 Program Memory Page Erase Control Register Interrupt Enable Register 0 Interrupt Priority Register 0 Serial Port 0, Reload Register, low byte ADC control register 1 ADC control register 2 ADC high data byte ADC low data byte Clock range register Port 3 PWM channel 2 data high byte PWM channel 2 data low byte PWM channel 3 data high byte PWM channel 3 data low byte PWM control register Watchdog timer control register Watchdog timer refresh key. Interrupt Enable Register 1 Interrupt Priority Register 1 Serial Port 0, Reload Register, high byte Serial Port 1, Reload Register, high byte PWM channel 0 data high byte PWM channel 0 data low byte PWM channel 1 data high byte PWM channel 1 data low byte Interrupt Request Control Register Compare/Capture Enable Register Compare/Capture Register 1, low byte Compare/Capture Register 1, high byte Compare/Capture Register 2, low byte
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 8 Ver.B SM59R16A2/SM59R08A2 06/2009
SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded Register CCH2 CCL3 CCH3 T2CON CRCL CRCH TL2 TH2 PSW BRGS ACC P4 MD0 MD1 MD2 MD3 MD4 MD5 ARCON B SPIC1 SPIC2 SPITxD SPIRxD SPIS IICS IICCTL IICA1 IICA2 IICRWD Location C5h C6h C7h C8h CAh CBh CCh CDh D0h D8h E0h E8h E9h EAh EBh ECh EDh EEh EFh F0h F1h F2h F3h F4h F5h F8h F9h FAh FBh FCh Reset value 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h FFh 00h 00h 00h 00h 00h 00h 00h 00h 08h 00h 00h 00h 40h 00h 04h A0h 60h 00h Description Compare/Capture Register 2, high byte Compare/Capture Register 3, low byte Compare/Capture Register 3, high byte Timer 2 Control Compare/Reload/Capture Register, low byte Compare/Reload/Capture Register, high byte Timer 2, low byte Timer 2, high byte Program status word Baud rate generator switch Accumulator Port 4 Multiplication/Division Register 0 Multiplication/Division Register 1 Multiplication/Division Register 2 Multiplication/Division Register 3 Multiplication/Division Register 4 Multiplication/Division Register 5 Arithmetic Control register B register
SPI control register 1 SPI control register 2
SPI transmit data buffer SPI receive data buffer SPI status register IIC status register IIC control register IIC Address 1 register IIC Address 2 register IIC Read/Write register
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 9 Ver.B SM59R16A2/SM59R08A2 06/2009
SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded
Function Description
1 General Features All of its functions and the detailed meanings
SM59R16A2/SM59R08A2 is an 8-bit micro-controller. of SFR will be given in the following sections. 1.1 Embedded Flash
The program can be loaded into the embedded 64KB/32KB Flash memory via its writer or In-System Programming (ISP).The high-quality Flash has a 100K-write cycle life, suitable for re-programming and data recording as EEPROM. 1.2 IO Pads The IO pads are compatible to the 8052 series. P0 is open-drain in the input or output high condition, so the external pull-up resistor is required. P1 ~ P5 are designed with internal pull-up resistors. The IO pad structure is given below:
Fig. 1-1: IO pad structure All the pads for P0 ~ P5 are with slew rate to reduce EMI. The other way to reduce EMI is to disable the ALE output if unused. This is selected by its SFR. The IO pads can withstand 4KV ESD in human body mode guaranteeing the SM59R16A2/SM59R08A2's quality in high electro-static environments. 1.3 2T/1T Selection The conventional 52-series MCUs are 12T, i.e., 12 oscillator clocks per machine cycle. SM59R16A2/SM59R08A2 is a 2T or 1T MCU, i.e., its machine cycle is two-clock or one-clock. In the other words, it can execute one instruction within two clocks or only one clock. The difference between 2T mode and 1T mode are given in the example in Fig. 1-2.
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 10 Ver.B SM59R16A2/SM59R08A2 06/2009
SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded
Fig. 1-2(a): The waveform of internal instruction signal in 2T mode
Fig. 1-2(b): The waveform of internal instruction signal in 1T mode The default is in 2T mode, and it can be changed to 1T mode if IFCON [7] (at address 8Fh) is set to high any time. Not every instruction can be executed with one machine cycle. The exact machine cycle number for all the instructions are given in the next section. 1.4 Reset Brownout detection is also one type of internal reset to prevent SM59R16A2/SM59R08A2 from going to unstable condition as described in Section 1.3. 1.5 Clocks The default clock is the 1MHz clock signal coming from the internal OSC. This clock is used during the initialization stage. The major work of the initialization stage is to determine the clock source used in normal operation. The clock source can be external and internal. The external clock source is from the crystal via crystal pads XTAL1 and XTA2, or oscillator through XTAL1 only. Here we need to be aware that XTAL1 are not 5V tolerant in 3.3V application, so a 3.3V oscillator source is recommended. The internal clock sources are from the internal OSC with difference frequency division as given in the next table: Table 1-1: Selection of clock source
Clock source external crystal or internal OSC 24MHz from internal OSC 20MHz from internal OSC 16MHz from internal OSC 12MHz from internal OSC 8MHz from internal OSC 4MHz from internal OSC 2MHz from internal OSC 1MHz from internal OSC as default clock used in initialization
There may be 20% variance in the frequency from the internal OSC. them in the application requiring accurate frequency.
It is not recommended to use
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 11 Ver.B SM59R16A2/SM59R08A2 06/2009
SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded
2
Instruction Set
All SM59R16A2/SM59R08A2 instructions are binary code compatible and perform the same functions as they do with the industry standard 8051. The following tables give a summary of the instruction set cycles of the SM59R16A2/SM59R08A2 Microcontroller core. Here the "cycles" in the tables means machine cycle, which is two-clock or one-clock depending on IFCON [7]. Table 2-1: Arithmetic operations
Mnemonic ADD A, Rn ADD A, direct ADD A, @Ri ADD A, #data ADDC A, Rn ADDC A, direct ADDC A, @Ri ADDC A, #data SUBB A, Rn SUBB A, direct SUBB A, @Ri SUBB A, #data INC A INC Rn INC direct INC @Ri INC DPTR DEC A DEC Rn DEC direct DEC @Ri MUL AB DIV DA A Description Add register to accumulator Add direct byte to accumulator Add indirect RAM to accumulator Add immediate data to accumulator Add register to accumulator with carry flag Add direct byte to A with carry flag Add indirect RAM to A with carry flag Add immediate data to A with carry flag Subtract register from A with borrow Subtract direct byte from A with borrow Subtract indirect RAM from A with borrow Subtract immediate data from A with borrow Increment accumulator Increment register Increment direct byte Increment indirect RAM Increment data pointer Decrement accumulator Decrement register Decrement direct byte Decrement indirect RAM Multiply A and B Divide A by B Decimal adjust accumulator Code 28-2F 25 26-27 24 38-3F 35 36-37 34 98-9F 95 96-97 94 04 08-0F 05 06-07 A3 14 18-1F 15 16-17 A4 84 D4 Bytes 1 2 1 2 1 2 1 2 1 2 1 2 1 1 2 1 1 1 1 2 1 1 1 1 Cycles 1 2 2 2 1 2 2 2 1 2 2 2 1 2 3 3 1 1 2 3 3 5 5 1
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 12 Ver.B SM59R16A2/SM59R08A2 06/2009
SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded
Table 2-2: Logic operations
Mnemonic ANL A, Rn ANL A, direct ANL A, @Ri ANL A, #data ANL direct, A ANL direct, #data ORL A, Rn ORL A, direct ORL A, @Ri ORL A, #data ORL direct, A ORL direct, #data XRL A, Rn XRL A, direct XRL A, @Ri XRL A, #data XRL direct, A XRL direct, #data CLR A CPL A RL A RLC A RR A RRC A SWAP A Description AND register to accumulator AND direct byte to accumulator AND indirect RAM to accumulator AND immediate data to accumulator AND accumulator to direct byte AND immediate data to direct byte OR register to accumulator OR direct byte to accumulator OR indirect RAM to accumulator OR immediate data to accumulator OR accumulator to direct byte OR immediate data to direct byte Exclusive OR register to accumulator Exclusive OR direct byte to accumulator Exclusive OR indirect RAM to accumulator Exclusive OR immediate data to accumulator Exclusive OR accumulator to direct byte Exclusive OR immediate data to direct byte Clear accumulator Complement accumulator Rotate accumulator left Rotate accumulator left through carry Rotate accumulator right Rotate accumulator right through carry Swap nibbles within the accumulator Code 58-5F 55 56-57 54 52 53 48-4F 45 46-47 44 42 43 68-6F 65 66-67 64 62 63 E4 F4 23 33 03 13 C4 Bytes 1 2 1 2 2 3 1 2 1 2 2 3 1 2 1 2 2 3 1 1 1 1 1 1 1 Cycles 1 2 2 2 3 4 1 2 2 2 3 4 1 2 2 2 3 4 1 1 1 1 1 1 1
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 13 Ver.B SM59R16A2/SM59R08A2 06/2009
SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded
Table 2-3: Data transfer
Mnemonic MOV A, Rn MOV A, direct MOV A, @Ri MOV A, #data MOV Rn, A MOV Rn, direct MOV Rn, #data MOV direct, A MOV direct, Rn MOV direct1, direct2 MOV direct, @Ri MOV direct, #data MOV @Ri, A MOV @Ri, direct MOV @Ri, #data MOV DPTR,#data16 MOVC A,@A+DPTR MOVC A, @A+PC MOVX A, @Ri MOVX A, @DPTR MOVX @Ri, A MOVX @DPTR, A PUSH direct POP direct XCH A, Rn XCH A, direct XCH A, @Ri XCHD A, @Ri Description Move register to accumulator Move direct byte to accumulator Move indirect RAM to accumulator Move immediate data to accumulator Move accumulator to register Move direct byte to register Move immediate data to register Move accumulator to direct byte Move register to direct byte Move direct byte to direct byte Move indirect RAM to direct byte Move immediate data to direct byte Move accumulator to indirect RAM Move direct byte to indirect RAM Move immediate data to indirect RAM Load data pointer with a 16-bit constant Move code byte relative to DPTR to accumulator Move code byte relative to PC to accumulator Move Expanded RAM (8-bit addr.) to A Move Expanded RAM (16-bit addr.) to A Move A to Expanded RAM (8-bit addr.) Move A to Expanded RAM (16-bit addr.) Push direct byte onto stack Pop direct byte from stack Exchange register with accumulator Exchange direct byte with accumulator Exchange indirect RAM with accumulator Exchange low-order nibble indir. RAM with A Code E8-EF E5 E6-E7 74 F8-FF A8-AF 78-7F F5 88-8F 85 86-87 75 F6-F7 A6-A7 76-77 90 93 83 E2-E3 E0 F2-F3 F0 C0 D0 C8-CF C5 C6-C7 D6-D7 Bytes 1 2 1 2 1 2 2 2 2 3 2 3 1 2 2 3 1 1 1 1 1 1 2 2 1 2 1 1 Cycles 1 2 2 2 2 4 2 3 3 4 4 3 3 5 3 3 3 3 3 3 4 4 4 3 2 3 3 3
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 14 Ver.B SM59R16A2/SM59R08A2 06/2009
SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded
Table 2-4: Program branches
Mnemonic ACALL addr11 LCALL addr16 RET RETI AJMP addr11 LJMP addr16 SJMP rel JMP @A+DPTR JZ rel JNZ rel JC rel JNC JB bit, rel JNB bit, rel JBC bit, direct rel CJNE A, direct rel CJNE A,#data rel CJNE Rn, #data rel CJNE @Ri, #data rel DJNZ Rn, rel DJNZ direct, rel NOP Description Absolute subroutine call Long subroutine call from subroutine from interrupt Absolute jump Long jump Short jump (relative addr.) Jump indirect relative to the DPTR Jump if accumulator is zero Jump if accumulator is not zero Jump if carry flag is set Jump if carry flag is not set Jump if direct bit is set Jump if direct bit is not set Jump if direct bit is set and clear bit Compare direct byte to A and jump if not equal Compare immediate to A and jump if not equal Compare immediate to reg. and jump if not equal Compare immediate to indirect and jump if not equal Decrement register and jump if not zero Decrement direct byte and jump if not zero No operation Code xxx11 12 22 32 xxx01 02 80 73 60 70 40 50 20 30 10 B5 B4 B8-BF B6-B7 D8-DF D5 00 Bytes 2 3 1 1 2 3 2 1 2 2 2 2 3 3 3 3 3 3 3 2 3 1 Cycles 6 6 4 4 3 4 3 2 3 3 3 3 4 4 4 4 4 4 4 3 4 1
Table 2-5: Boolean manipulation
Mnemonic CLR C CLR bit SETB C SETB bit CPL C CPL bit ANL C, bit ANL C, /bit ORL C, bit ORL C, /bit MOV C, bit MOV bit, C Description Clear carry flag Clear direct bit Set carry flag Set direct bit Complement carry flag Complement direct bit AND direct bit to carry flag AND complement of direct bit to carry OR direct bit to carry flag OR complement of direct bit to carry Move direct bit to carry flag Move carry flag to direct bit Code C3 C2 D3 D2 B3 B2 82 B0 72 A0 A2 92 Bytes 1 2 1 2 1 2 2 2 2 2 2 2 Cycles 1 3 1 3 1 3 2 2 2 2 2 3
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 15 Ver.B SM59R16A2/SM59R08A2 06/2009
SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded
3
Memory Structure
The SM59R16A2/SM59R08A2 memory structure follows general 8052 structures. It manipulates operands in three memory spaces. They are (1) 256 bytes standard RAM, (2) 2K bytes auxiliary RAM, and (3) 64K/32K bytes embedded Flash as program memory. 3.1 Program Memory The SM59R16A2/SM59R08A2 has 64KB/32KB on-chip Flash memory, which can be used as general program memory. If there is any byte not used as program memory, it can be used to record any data as EEPROM. The detailed way is given in Section 17.
FFFF
64KB program memory space
7FFF
32KB program memory space
0000
Fig. 3-1: 32KB/64KB programmable Flash 3.2 Data Memory SM59R16A2/SM59R08A2 has 2048 + 256Bytes on-chip SRAM, the 256 bytes are the same as general 8052 internal memory structure. The expanded 2KB on-chip SRAM can be accessed by external memory addressing method (by instruction MOVX). As for 2KB - 64KB (Address 0800h - FFFFh) memory, they must be accessed as the external one through the interface similar to the conventional interface (P2, P0 are as the address and data bus, P3 [7:6] indicates read or write). If the SFR IFCON [1] = 1, this 2KB on-chip SRAM will be disabled and all the data memory are accessed externally. Even though this MCU is 2T or 1T, the external memory interface is still similar to the conventional 12T ways. An example is given below:
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 16 Ver.B SM59R16A2/SM59R08A2 06/2009
SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded
Fig 3-2 (a)External memory access as read
Fig 3-2 (b)External memory access as write
Fig. 3-3: RAM architecture 3.2.1 Data memory - lower 128 byte (00h to 7Fh)
Data Memory 00h to FF is the same as defined in 8052. The address 00h to 7Fh can be accessed by both direct and indirect addressing modes. Address 00h to 1Fh is register area. Address 20h to 2Fh is memory bit area, and address 30h to 7Fh is for general memory area.
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 17 Ver.B SM59R16A2/SM59R08A2 06/2009
SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded
3.2.2
Data memory - higher 128 byte (80h to FFh) It is data area.
The address 80h to FFh can only be accessed by indirect addressing mode. 3.2.3 Data memory - Expanded 2048 bytes ($0000 to $07FF)
From external address 0000h to 07FFh is the on-chip expanded SRAM area, total 2048 Bytes. This area can be accessed by external direct addressing mode (by instruction MOVX). If the address of instruction MOVX @DPTR is larger than 07FFhthe SM59R16A2 will generate the external memory control signal automatically. If the SFR IFCON [1] = 1, this 2KB on-chip SRAM will be disabled as if there is no such embedded memory. The default value for IFCON [1] is 0.
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 18 Ver.B SM59R16A2/SM59R08A2 06/2009
SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded
4
CPU Engine
The SM59R16A2/SM59R08A2 engine is composed of four components: a. Control unit b. Arithmetic - logic unit c. Memory control unit d. RAM and SFR control unit The SM59R16A2/SM59R08A2 engine allows to fetch instruction from program memory and to execute using RAM or SFR. The following paragraphs describe the main engine registers.
Mnemonic ACC B PSW SP DPL DPH DPL1 DPH1 DPS IFCON Description Accumulator B register Program status word Stack Pointer Data pointer low 0 Data pointer high 0 Data pointer low 1 Data pointer high 1 Data pointer select Interface control register
Direct
Bit 7 ACC.7 B.7 CY
E0h F0h D0h 81h 82h 83h 84h 85h 92h 8Fh
Bit 6 Bit 5 CPU Core ACC.6 ACC.5 B.6 B.5 AC F0
Bit 4 ACC.4 B.4
Bit 3 ACC.3 B.3
Bit 2 ACC.2 B.2 OV
Bit 1 ACC.1 B.1
F1
Bit 0 ACC.0 B.0 P
RESET 00h 00h 00h 07h 00h 00h 00h 00h 00h 00h
RS [1:0] SP [7:0] DPL [7:0] DPH [7:0] DPL1 [7:0] DPH1 [7:0] -
ITS
-
-
-
DMEN
DPS.0 -
ALEC[1:0]
4.1 Accumulator ACC is the Accumulator register. Most instructions use the accumulator to store the operand.
Mnemonic: ACC 7 6 ACC.7 ACC.6 5 ACC05 4 ACC.4 3 ACC.3 2 ACC.2 1 ACC.1 Address: E0h 0 Reset ACC.0 00h
ACC[7:0]: The A (or ACC) register is the standard 8052 accumulator.
4.2 B Register The B register is used during multiply and divide instructions. It can also be used as a scratch pad register to store temporary data.
Mnemonic: B 7 6 B.7 B.6 5 B.5 4 B.4 3 B.3 2 B.2 1 B.1 Address: F0h 0 Reset B.0 00h
B[7:0]: The B register is the standard 8052 register that serves as a second accumulator.
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 19 Ver.B SM59R16A2/SM59R08A2 06/2009
SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded
4.3 Program Status Word
Mnemonic: PSW 7 6 CY AC 5 F0 4 RS [1:0] 3 2 OV 1 F1 Address: D0h 0 Reset P 00h
CY: Carry flag. AC: Auxiliary Carry flag for BCD operations. F0: General purpose Flag 0 available for user. RS[1:0]: Register bank select, used to select working register bank. RS[1:0] Bank Selected Location 00 Bank 0 00h - 07h 01 Bank 1 08h - 0Fh 10 Bank 2 10h - 17h 11 Bank 3 18h - 1Fh OV: Overflow flag. F1: General purpose Flag 1 available for user. P: Parity flag, affected by hardware to indicate odd/even number of "one" bits in the Accumulator, i.e. even parity.
4.4 Stack Pointer The stack pointer is a 1-byte register initialized to 07h after reset. This register is incremented before PUSH and CALL instructions, causing the stack to start from location 08h.
Mnemonic: SP 7 6 5 4 SP [7:0] 3 2 1 Address: 81h 0 Reset 07h
SP[7:0]: The Stack Pointer stores the scratchpad RAM address where the stack begins. In other words, it always points to the top of the stack.
4.5 Data Pointer The data pointer (DPTR) is 2-bytes wide. The lower part is DPL, and the highest is DPH. It can be loaded as a 2-byte register (e.g. MOV DPTR, #data16) or as two separate registers (e.g. MOV DPL,#data8). It is generally used to access the external code or data space (e.g. MOVC A, @A+DPTR or MOVX A, @DPTR respectively).
Mnemonic: DPL 7 6 5 4 3 DPL [7:0] 2 1 Address: 82h 0 Reset 00h
DPL[7:0]: Data pointer Low 0 Mnemonic: DPH 7 6 Address: 83h 0 Reset 00h
5
4
3 DPH [7:0]
2
1
DPH [7:0]: Data pointer High 0
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 20 Ver.B SM59R16A2/SM59R08A2 06/2009
SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded
4.6 Data Pointer 1 The dual data pointer accelerates the moving of block data. The standard DPTR is a 16-bit register that is used to address external memory or peripherals. In the SM59R16A2/SM59R08A2, the standard data pointer is called DPTR, the second data pointer is called DPTR1. The data pointer select bit chooses the active pointer. The data pointer select bit is located in the LSB of DPS register (DPS.0). The user switches the pointer between PDTR and DPTR1 by toggling the LSB of DPS register. All DPTR-related instructions use the currently selected DPTR for any activity.
Mnemonic: DPL1 7 6 5 4 3 DPL1 [7:0] 2 1 Address: 84h 0 Reset 00h
DPL1[7:0]: Data pointer Low 1 Mnemonic: DPH1 7 6 Address: 85h 0 Reset 00h
5
4 3 DPH1 [7:0]
2
1
DPH1[7:0]: Data pointer High 1 Mnemonic: DPS 7 6 Address: 92h 0 Reset DPS.0 00h
5 -
4 -
3 -
2 -
1 -
DPS.0: Data Pointer selects register. DPS.0 = 1 is selected DPTR1.
4.7 Interface control register
Mnemonic: IFCON 7 6 ITS 5 4 3 2 ALEC[1:0] 1 DMEN Address: 8Fh 0 Reset 00h
ITS: Instruction timing select. ITS = 0, 2T instruction mode. ITS = 1, 1T instruction mode. ALEC[1:0]: ALE output control register. ALEC[1:0] ALE Output 00 Always output 01 No ALE output 10 Only Read or Write have ALE output 11 reserved DMEN: Internal 2K SRAM disable.(default is enable) DMEN = 0, Enable internal 2K RAM. DMEN = 1, Disable internal 2K RAM.
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 21 Ver.B SM59R16A2/SM59R08A2 06/2009
SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded
5
Port0 - Port 5
Port 0 ~ Port 5 are the general purpose IO of this controller. Most of the ports are multiplexed with the other outputs, e.g., Port 3[0] is also used as RXD in the UART application. Port0 is open-drain in the input and output high condition; so external pull-up resistors are required. As for the other ports, the pull-up resistors are built internally. For general-purpose applications, every pin can be assigned to either high or low independently as given below:
Mnemonic Port 5 Port 4 Port 3 Port 2 Port 1 Port 0 Description Port 5 Port 4 Port 3 Port 2 Port 1 Port 0 Direct 91h E8h B0h A0h 90h 80h Bit 7 P5.7 P4.7 P3.7 P2.7 P1.7 P0.7 Bit 6 P5.6 P4.6 P3.6 P2.6 P1.6 P0.6 Bit 5 Ports P5.5 P4.5 P3.5 P2.5 P1.5 P0.5 Bit 4 P5.4 P4.4 P3.4 P2.4 P1.4 P0.4 Bit 3 P5.3 P4.3 P3.3 P2.3 P1.3 P0.3 Bit 2 P5.2 P4.2 P3.2 P2.2 P1.2 P0.2 Bit 1 P5.1 P4.1 P3.1 P2.1 P1.1 P0.1 Bit 0 P5.0 P4.0 P3.0 P2.0 P1.0 P0.0 RESET FFh FFh FFh FFh FFh FFh
Mnemonic: P0 7 6 P0.7 P0.6
5 P0.5
4 P0.4
3 P0.3
2 P0.2
1 P0.1
Address: 80h 0 Reset P0.0 FFh
P0.7~ 0: Port0 [7] ~ Port0 [0] Mnemonic: P1 7 6 P1.7 P1.6 Address: 90h 0 Reset P1.0 FFh
5 P1.5
4 P1.4
3 P1.3
2 P1.2
1 P1.1
P1.7~ 0: Port1 [7] ~ Port1 [0] Mnemonic: P2 7 6 P2.7 P2.6 Address: A0h 0 Reset P2.0 FFh
5 P2.5
4 P2.4
3 P2.3
2 P2.2
1 P2.1
P2.7~ 0: Port2 [7] ~ Port2 [0] Mnemonic: P3 7 6 P3.7 P3.6 Address: B0h 0 Reset P3.0 FFh
5 P3.5
4 P3.4
3 P3.3
2 P3.2
1 P3.1
P3.7~ 0: Port3 [7] ~ Port3 [0] Mnemonic: P4 7 6 P4.7 P4.6 Address: E8h 0 Reset P4.0 FFh
5 P4.5
4 P4.4
3 P4.3
2 P4.2
1 P4.1
P4.7~ 0: Port4 [7] ~ Port4 [0] Mnemonic: P5 7 6 P5.7 P5.6 Address: 91h 0 Reset P5.0 FFh
5 P5.5
4 P5.4
3 P5.3
2 P5.2
1 P5.1
P5.7~ 0: Port5 [7] ~ Port5 [0] Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 22 Ver.B SM59R16A2/SM59R08A2 06/2009
SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded
6
Multiplication Division Unit (MDU)
This on-chip arithmetic unit provides 32-bit division, 16-bit multiplication, shift and normalize features, etc. All operations are unsigned integer operations.
Mnemonic PCON ARCON MD0 MD1 MD2 MD3 MD4 MD5 Description Power control Arithmetic Control register Multiplication/Div ision Register 0 Multiplication/Div ision Register 1 Multiplication/Div ision Register 2 Multiplication/Div ision Register 3 Multiplication/Div ision Register 4 Multiplication/Div ision Register 5 Direct 87h EFh E9h EAh EBh ECh EDh EEh Bit 6 Bit 5 Bit 4 Multiplication Division Unit SMOD MDUF PMW MDEF MDOV SLR MD0 [7:0] MD1 [7:0] MD2 [7:0] MD3 [7:0] MD4 [7:0] MD5 [7:0] Bit 7 Bit 3 Bit 2 SC [4:0] Bit 1 STOP Bit 0 IDLE RESET 00h 00h 00h 00h 00h 00h 00h 00h
6.1
Operation of the MDU
The operation of the MDU consists of three phases: 6.1.1 First phase: loading the MDx registers, x = 0~5:
The type of calculation the MDU has to perform is selected by the order in which the MDx registers are written to. A write to MD0 is the first transfer to be done in any case. Next writes must be done as shown in table below to determine MDU operation. The last write will start the selected operation. Table 6-1: MDU registers write sequence
Operation First write 32bit/16bit MD0 Dividend Low MD1 Dividend MD2 Dividend MD3 Dividend High MD4 Divisor Low MD5 Divisor High 16bit/16bit MD0 Dividend Low MD1 Dividend High 16bit x 16bit MD0 Multiplicand Low MD4 Multiplicator Low MD1 Multiplicand High shift/normalizing MD0 LSB MD1 MD2 MD3 MSB ARCON start conversion
Last write
MD4 Divisor Low MD5 Divisor High
MD5 Multiplicator High
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 23 Ver.B SM59R16A2/SM59R08A2 06/2009
SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded
6.1.2
Second phase: executing calculation.
During executing operation, the MDU works on its own parallel to the CPU. When MDU is finished, the MDUF register will be set to one by hardware and the flag will be cleared at the next calculation.
Mnemonic: PCON 7 6 SMOD MDUF 5 4 PMW 3 2 1 STOP Address: 87h 0 Reset IDLE 00h
MDUF: MDU finish flag. When MDU is finished, the MDUF will be set by hardware and the bit will clear by hardware at next calculation.
The following table gives the execution time in every mathematical operation. Table 6-2: MDU execution times
Operation Division 32bit/16bit Division 16bit/16bit Multiplication Shift Normalize Number of Tclk 17 clock cycles 9 clock cycles 11 clock cycles Min. 3 clock cycles, Max. 18 clock cycles Min. 4 clock cycles, Max. 19 clock cycles
6.1.3
Third phase: reading the result from the MDx registers.
The sequence of reading out the first MDx registers is not critical, but we have to be aware that the last read (from MD5 in division operation, or MD3 by multiplication, shift and normalizing) means the end of a whole calculation. Table 6-3: MDU registers read sequence
Operation First read 32Bit/16Bit MD0 Quotient Low MD1 Quotient MD2 Quotient MD3 Quotient High MD4 Remainder L MD5 Remainder H 16Bit/16Bit MD0 Quotient Low MD1 Quotient High 16Bit x 16Bit MD0 Product Low MD1 Product MD2 Product shift/normalizing MD0 LSB MD1 MD2
Last read
MD4 Remainder Low MD5 Remainder High
MD3 Product High
MD3 MSB
Here the operation of normalization and shift will be explained more. In normalization, all reading zeroes in registers MD0 to MD3 are removed by shift left. The whole operation is completed when the MSB (most significant bit) of MD3 register contains a '1'. After normalizing, bits ARCON.4 (MSB) to ARCON.0 (LSB) contain the number of shift left operations. As for shift, SLR bit (ARCON.5) has to contain the shift direction, and ARCON.4 to ARCON.0 represent the shift count (which must not be 0). During shift, zeroes come into the left or right end of the registers MD0 or MD3, respectively.
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 24 Ver.B SM59R16A2/SM59R08A2 06/2009
SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded
6.2 Operating registers The MDU is handled by seven registers, which are memory mapped as special function registers. The arithmetic unit allows operations concurrently to and independent of the CPU's activity. Operands and results registers are MD0 to MD5, and the control register is ARCON. Any calculation of the MDU will overwrite its operands.
Mnemonic: ARCON 7 6 5 MDEF MDOV SLR 4 3 2 SC [4:0] 1 Address: EFh 0 Reset 00h
MDEF: Multiplication Division Error Flag. The MDEF is an error flag. The error flag is read only. The error flag indicates an improperly performed operation (when one of the arithmetic operations has been restarted or interrupted by a new operation). The error flag mechanism is automatically enabled with the first write to MD0 and disabled with the final read instruction from MD3 (multiplication or shift/normalizing) or MD5 (division) in the third phase. The error flag is set when: 1. The second phase in process and write access to MDx registers (restart or interrupt calculations) The error flag is reset only if: The second phase finished (arithmetic operation successful completed) and read access to MDx registers. MDOV: Multiplication Division Overflow flag. The overflow flag is read only. The overflow flag is set when: Divided by zero Multiplication with a result greater then 0000FFFFh Start of normalizing if the most significant bit of MD3 is set (MD3.7=1) The overflow flag is reset when: Write access to MD0 register (start the first phase) SLR: Shift direction bit. SLR = 0 - shift left operation. SLR = 1 - shift right operation. SC [4:0]: Shift counter. When preset with 00000b, normalizing is selected. After normalized, SC[4:0] contains the number of normalizing shifts performed. When SC[4:0] 0, shift operation is started. The number of shifts performed is determined by the count written to SC [4:0]. SC [4] is MSB and SC[0] is LSB.
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 25 Ver.B SM59R16A2/SM59R08A2 06/2009
SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded
7
Timer 0 and Timer 1
SM59R16A2/SM59R08A2 has three 16-bit timer/counter registers: Timer 0, Timer 1 and Timer 2. All can be configured for counter or timer operations. In timer mode, the Timer 0 register or Timer 1 register is incremented every 12 machines cycles, which means that it counts up after every 12 periods of the crystal or oscillator signal. In counter mode, the register is incremented when the falling edge is observed at the corresponding input pin T0 or T1. Since it takes 2 machine cycles to recognize a 1-to-0 event, the maximum input count rate is 1/2 of the oscillator frequency. There are no restrictions on the duty cycle to ensure proper recognition of 0 or 1 state, so an input should be stable for at least 1 machine cycle. Four operating modes can be selected for Timer 0 and Timer 1. Two SFRs (TMOD and TCON) are used to select the appropriate mode.
Mnemonic TL0 TH0 TL1 TH1 TMOD TCON Description Timer 0 , low byte Timer 0 , high byte Timer 1 , low byte Timer 1 , high byte Timer Mode Control Timer/Counter Control
Direct
Bit 7
Bit 6 Bit 5 Timer 0 and 1
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESET 00h 00h 00h 00h
8Ah 8Ch 8Bh 8Dh 89h 88h GATE TF1 C/T TR1 M1 TF0
TL0[7:0] TH0[7:0] TL1[7:0] TH1[7:0] M0 TR0 GATE IE1 C/T IT1 M1 IE0 M0 IT0
00h 00h
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 26 Ver.B SM59R16A2/SM59R08A2 06/2009
SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded
7.1 Timer/counter mode control register (TMOD)
Mnemonic: TMOD 7 6 5 GATE C/T M1 Timer 1 4 M0 3 GATE 2 1 C/T M1 Timer 0 Address: 89h 0 Reset M0 00h
GATE: If set, enables external gate control (pin INT0 or INT1 for Counter 0 or 1, respectively). When INT0 or INT1 is high, and TRx bit is set (see TCON register), a counter is incremented every falling edge on T0 or T1 input pin C/T: Selects Timer or Counter operation. When set to 1, a counter operation is performed, when cleared to 0, the corresponding register will function as a timer. M[1:0]: Selects mode for Timer/Counter 0 or Timer/Counter 1. M1 M0 Mode Function 0 0 Mode0 13-bit counter/timer, with 5 lower bits in TL0 or TL1 register and 8 bits in TH0 or TH1 register (for Timer 0 and Timer 1, respectively). The 3 high order bits of TL0 and TL1 are hold at zero. 0 1 Mode1 16-bit counter/timer. 1 0 Mode2 8 -bit auto-reload counter/timer. The reload value is kept in TH0 or TH1, while TL0 or TL1 is incremented every machine cycle. When TLx overflows, a value from THx is copied to TLx. 1 1 Mode3 If Timer 1 M1 and M0 bits are set to 1, Timer 1 stops. If Timer 0 M1 and M0 bits are set to 1, Timer 0 acts as two independent 8 bit timers / counters.
7.2
Timer/counter control register (TCON)
Mnemonic: TCON 7 6 5 TF1 TR1 TF0 4 TR0 3 IE1 2 IT1 1 IE0 Address: 88h 0 Reset IT0 00h
TF1: Timer 1 overflow flag set by hardware when Timer 1 overflows. This flag can be cleared by software and is automatically cleared when interrupt is processed. TR1: Timer 1 Run control bit. If cleared, Timer 1 stops. TF0: Timer 0 overflow flag set by hardware when Timer 0 overflows. This flag can be cleared by software and is automatically cleared when interrupt is processed. TR0: Timer 0 Run control bit. If cleared, Timer 0 stops. IE1: Interrupt 1 edge flag. Set by hardware, when falling edge on external pin INT1 is observed. Cleared when interrupt is processed. IT1: Interrupt 1 type control bit. Selects falling edge or low level on input pin to cause interrupt. IE0: Interrupt 0 edge flag. Set by hardware, when falling edge on external pin INT0 is observed. Cleared when interrupt is processed. IT0: Interrupt 0 type control bit. Selects falling edge or low level on input pin to cause interrupt.
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 27 Ver.B SM59R16A2/SM59R08A2 06/2009
SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded
8
Timer 2 and Capture/Compare Unit
Timer 2 is not only a 16-bit timer, also a 4-channel unit with compare, capture and reload functions. It is very similar to the programmable counter array (PCA) in some other MCUs except pulse width modulation (PWM).
Mnemonic T2CON CCEN TL2 TH2 CRCL Description Timer 2 control Compare/Capture Enable register Timer 2, low byte Timer 2, high byte Compare/Reload/ Capture register, low byte Compare/Reload/ Capture register, high byte Compare/Capture register 1, low byte Compare/Capture register 1, high byte Compare/Capture register 2, low byte Compare/Capture register 2, high byte Compare/Capture register 3, low byte Compare/Capture register 3, high byte
Direct
C8h C1h CCh CDh CAh
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Timer 2 and Capture Compare Unit T2PS CC0FR T2R[1:0] COCA COCA COC COCA COCA H3 L3 AH2 L2 H1 TL2[7:0] TH2[7:0] CRCL[7:0]
Bit 2 T2CM COCA L1
Bit 1
Bit 0
RESET 00h 00h 00h 00h 00h
T2I[1:0] COCA COC H0 AL0
00h CBh CRCH[7:0] 00h C2h CCL1[7:0] 00h C3h CCH1[7:0] 00h C4h CCL2[7:0] 00h C5h CCH2[7:0] 00h C6h CCL3[7:0] 00h C7h CCH3[7:0]
CRCH
CCL1
CCH1
CCL2
CCH2
CCL3
CCH3
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 28 Ver.B SM59R16A2/SM59R08A2 06/2009
SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded
Mnemonic: T2CON 7 6 T2PS CC0FR
5 -
4
3 T2R[1:0]
2 T2CM
1
Address: C8h 0 Reset T2I[1:0] 00h
T2PS: Prescaler select bit: T2PS = 0 - timer 2 is clocked with 1/12 of the oscillator frequency. T2PS = 1 - timer 2 is clocked with 1/24 of the oscillator frequency. CC0FR: Select active edge: CC0FR = 0 - falling edge CC0FR = 1 - rising edge T2R[1:0]: Timer 2 reload mode selection T2R[1:0] = 0X - Reload disabled T2R[1:0] = 10 - Mode 0 T2R[1:0] = 11 - Mode 1 T2CM: Timer 2 Compare mode selection T2CM = 0 - Mode 0 T2CM = 1 - Mode 1 T2I[1:0]: Timer 2 input selection T2I[1:0] = 00 - Timer 2 stop T2I[1:0] = 01 - Input frequency f/12 or f/24 T2I[1:0] = 10 - Timer 2 is incremented by external signal at pin T2 T2I[1:0] = 11 - internal clock input is gated to the Timer 2 Mnemonic: CCEN 7 6 COCAH3 COCAL3 Address: C1h 0 Reset COCAL0 00h
5 COCAH2
4 COCAL2
3 COCAH1
2 COCAL1
1 COCAH0
COCAH3,COCAL3: Compare/capture mode for Channel 3. COCAH3 COCAL3 Function 0 0 Compare/capture disable 0 1 Capture on rising edge at pin CC3 1 0 Compare enable 1 1 Capture on write operation into register CCL3 COCAH2,COCAL2: Compare/Capture mode for Channel 2. COCAH3 COCAL3 Function 0 0 Compare/capture disable 0 1 Capture on rising edge at pin CC2 1 0 Compare enable 1 1 Capture on write operation into register CCL2 COCAH1,COCAL1: Compare/Capture mode for Channel 1. COCAH1 COCAL1 Function 0 0 Compare/capture disable 0 1 Capture on rising edge at pin CC1 1 0 Compare enable 1 1 Capture on write operation into register CCL1 COCAH0,COCAL0: Compare/Capture mode for CRC register (Channel 0) COCAH3 COCAL3 Function 0 0 Compare/capture disable 0 1 Capture on falling/rising edge at pin CC0 1 0 Compare enable 1 1 Capture on write operation into register CRCL
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 29 Ver.B SM59R16A2/SM59R08A2 06/2009
SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded
8.1 Timer 2 function Timer 2 can operate as timer, event counter, or gated timer as explained later. 8.1.1 Timer mode
In this mode Timer 2 can be incremented in every 12 machine cycles or in every 24 machine cycles depending on the 2:1 prescaler. The prescaler is selected by bit T2PS in register T2CON. 8.1.2 Event counter mode
In this mode, the timer is incremented when external signal T2 change value from 1 to 0. The T2 input is sampled in every cycle. Timer 2 is incremented in the cycle following the one in which the transition was detected. 8.1.3 Gated timer mode
In this mode, the internal clock which incremented timer 2 is gated by external signal T2. 8.1.4 Reload of Timer 2
Reload (16-bit reload from the crc register) can be executed in the following two modes: Mode 0: Reload signal is generate by a Timer 2 overflows - auto reload Mode 1: Reload signal is generate by a negative transition at the corresponding input pin T2EX. 8.2 Compare function
In the four independent comparators, the value stored in any compare/capture register is compared with the contents of the timer register. The compare modes 0 and 1 are selected by bit T2CM. In both compare modes, the results of comparison arrives at Port 1 within the same machine cycle in which the internal compare signal is activated. The port pins P1.2 to P1.5 are the outputs of CC0 to CC3. 8.2.1 Compare Mode 0
In mode 0, when the value in Timer 2 equals the value of the compare register, the output signal changes from low to high. It goes back to a low level on timer overflow. In this mode, writing to the port will have no effect, because the input line from the internal bus and the write-to-latch line are disconnected. The following figure illustrates the function of compare mode 0.
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 30 Ver.B SM59R16A2/SM59R08A2 06/2009
SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded
Fig. 8-1: Compare mode 0 function
8.2.2
Compare Mode 1
In compare mode 1, the transition of the output signal can be determined by software. A timer 2 overflow causes no output change. In this mode, both transitions of a signal can be controlled. Fig. 8-2 shows a functional diagram of a register/port configuration in compare Mode 1. In compare Mode 1, the value is written first to the "Shadow Register", when compare signal is active, this value is transferred to the output register. Fig. 8-2: Compare mode 1 function
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 31 Ver.B SM59R16A2/SM59R08A2 06/2009
SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded
8.3 Capture function Actual timer/counter contents can be saved into registers CCx or CRC upon an external event (mode 0) or a software write operation (mode 1). 8.3.1 Capture Mode 0
In mode 0, value capture of Timer 2 is executed when: (a) rising edge on input CC1-CC3 (b) rising or falling edge on input CC0 (depending on bit CC0FR) The contents of Timer 2 will be latched into the appropriate capture register. In this mode, no interrupt request will be generated. 8.3.2 Capture Mode 1
In mode 1, value capture of timer 2 is caused by writing any value into the low-order byte of the dedicated capture register. The value written to the capture register is irrelevant to this function. The contents of Timer 2 will be latched into the appropriate capture register. In this mode, no interrupt request will be generated.
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 32 Ver.B SM59R16A2/SM59R08A2 06/2009
SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded
9
Serial interface 0 and 1
There are two serial interfaces for data communication in SM59R16A2/SM59R08A2, they are the so called UART0 and UART1. As the conventional UART, the communication speed can be selected by configuring the baud rate in SFRs. These two serial buffers consists of two separate registers, a transmit buffer and a receive buffer. Writing data to the SFR S0BUF or S1BUF sets this data in serial output buffer and starts the transmission. Reading from the S0BUF or S1BUF reads data from the serial receive buffer. The serial port can simultaneously transmit and receive data. It can also buffer 1 byte at receive, which prevents the receive data from being lost if the CPU reads the second byte before the transmission of the first byte is completed.
Mnemonic PCON BRGS S0CON S0RELL Description Power control Baud rate generator switch Serial Port 0 control register Serial Port 0 reload register low byte Serial Port 0 reload register high byte Serial Port 0 data buffer Serial Port 1 control register Serial Port 1 reload register low byte Serial Port 1 reload register high byte Serial Port 1 data buffer
Direct
Bit 7 SMOD BRS SM0 S0REL .7 -
Bit 6
Bit 5
Bit 4
Bit 3 TB80 S0REL .3 -
Bit 2 RB80 S0REL .2 -
Bit 1 STOP TI0 S0REL .1 S0REL .9
Bit 0 IDLE RI0 S0REL .0 S0REL .8
RESE T 00h 00h 00h 00h
87h D8h 98h AAh
Serial interface 0 and 1 MDUF PMW SM1 S0REL .6 SM20 S0REL .5 REN0 S0REL .4 -
S0RELH S0BUF S1CON S1RELL
BAh 99h 9Bh 9Dh
00h 00h
S0BUF[7:0] SM S1REL .7 S1REL .6 SM21 S1REL .5 REN1 S1REL .4 TB81 S1REL .3 RB81 S1REL .2 TI1 S1REL .1 S1REL .9 RI1 S1REL .0 S1REL .8
00h 00h
S1RELH S1BUF
BBh 9Ch
00h 00h
S1BUF[7:0]
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 33 Ver.B SM59R16A2/SM59R08A2 06/2009
SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded
Mnemonic: S0CON 7 6 5 SM0 SM1 SM20
4 REN0
3 TB80
2 RB80
1 TI0
Address: 98h 0 Reset RI0 00h
SM0,SM1: Serial Port 0 mode selection. SM0 SM1 Mode 0 0 0 0 1 1 1 0 2 1 1 3 The 4 modes in UART0, Mode 0 ~ 3, are explained later. SM20: Enables multiprocessor communication feature REN0: If set, enables serial reception. Cleared by software to disable reception. TB80: The 9th transmitted data bit in modes 2 and 3. Set or cleared by the CPU depending on the function it performs such as parity check, multiprocessor communication etc. RB80: In modes 2 and 3, it is the 9th data bit received. In mode 1, if SM20 is 0, RB80 is the stop bit. In mode 0, this bit is not used. Must be cleared by software. TI0: Transmit interrupt flag, set by hardware after completion of a serial transfer. Must be cleared by software. RI0: Receive interrupt flag, set by hardware after completion of a serial reception. Must be cleared by software.
Mnemonic: S1CON 7 6 5 SM SM21
4 REN1
3 TB81
2 RB81
1 TI1
Address: 9Bh 0 Reset RI1 00h
SM: Serial Port 1 mode select. SM Mode 0 A 1 B The 2 modes in UART1, Mode A and Mode B, are explained later. SM21: Enables multiprocessor communication feature. REN1: If set, enables serial reception. Cleared by software to disable reception. TB81: The 9th transmitted data bit in mode A. Set or cleared by the CPU depending on the function it performs such as parity check, multiprocessor communication etc. RB81: In mode A, it is the 9th data bit received. In mode B, if SM21 is 0, RB81 is the stop bit. Must be cleared by software. TI1: Transmit interrupt flag, set by hardware after completion of a serial transfer. Must be cleared by software. RI1: Receive interrupt flag, set by hardware after completion of a serial reception. Must be cleared by software.
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 34 Ver.B SM59R16A2/SM59R08A2 06/2009
SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded
9.1 Serial interface 0 The Serial Interface 0 can operate in the following 4 modes:
SM0 0 0 1 1 SM1 0 1 0 1 Mode 0 1 2 3 Description Shift register 8-bit UART 9-bit UART 9-bit UART Board Rate Fosc/12 Variable Fosc/32 or Fosc/64 Variable
Here Fosc is the crystal or oscillator frequency. 9.1.1 Mode 0
Pin RXD0 serves as input and output. TXD0 outputs the shift clock. 8 bits are transmitted with LSB first. The baud rate is fixed at 1/12 of the crystal frequency. Reception is initialized in Mode 0 by setting the flags in S0CON as follows: RI0 = 0 and REN0 = 1. In the other modes, a start bit when REN0 = 1 starts receiving serial data.
Fig. 9-1: Transmit mode 0 for Serial 0
Fig. 9-2: Receive mode 0 for Serial 0 9.1.2 Mode 1
Here Pin RXD0 serves as input, and TXD0 serves as serial output. No external shift clock is used, 10 bits are transmitted: a start bit (always 0), 8 data bits (LSB first), and a stop bit (always 1). On receive, a start bit synchronizes the transmission, 8 data bits are available by reading S0BUF, and a stop bit sets the flag RB80 in the SFR S0CON. In mode 1, either internal baud rate generator or timer 1 can be use to specify the desired baud rate.
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 35 Ver.B SM59R16A2/SM59R08A2 06/2009
SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded
Fig. 9-3: Transmit mode 1 for Serial 0
Fig. 9-4: Receive mode 1 for Serial 0 9.1.3 Mode 2
This mode is similar to Mode 1, but with two differences. The baud rate is fixed at 1/32 (SMOD=1) or 1/64(SMOD=0) of oscillator frequency, and 11 bits are transmitted or received: a start bit (0), 8 data bits (LSB first), a programmable Bit 9, and a stop bit (1). Bit 9 can be used to control the parity of the serial interface: at transmission, bit TB80 in S0CON is output as Bit 9, and at receive, Bit 9 affects RB80 in SFR S0CON. 9.1.4 Mode 3
The only difference between Mode 2 and Mode 3 is that : in Mode 3, either internal baud rate generator or timer 1 can be use to specify baud rate.
Fig. 9-5: Transmit modes 2 and 3 for Serial 0
Fig. 9-6: Receive modes 2 and 3 for Serial 0
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 36 Ver.B SM59R16A2/SM59R08A2 06/2009
SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded
9.2
Serial interface 1
The Serial Interface 1 can operate in the following 2 modes:
SM 0 1 Mode A B Description 9-bit UART 8-bit UART Baud Rate Variable Variable
9.2.1
Mode A
This mode is similar to Mode 2 and 3 of Serial interface 0, 11 bits are transmitted or received: a start bit (0), 8 data bits (LSB first), a programmable Bit 9, and a stop bit (1). Bit 9 can be used to control the parity of the serial interface: at transmission, bit TB81 in S1CON is outputted as Bit 9, and at receive, Bit 9 affects RB81 in SFR S1CON.
Fig. 9-7: Transmit mode A for Serial 1
Fig. 9-8: Receive mode A for Serial 1 9.2.2 Mode B
This mode is similar to Mode 1 of Serial interface 0. Pin RXD1 serves as input, and TXD1 serves as serial output. No external shift clock is used. 10 bits are transmitted: a start bit (always 0), 8 data bits (LSB first), and a stop bit (always 1). On receive, a start bit synchronizes the transmission, 8 data bits are available by reading S1BUF, and stop bit sets the flag RB81 in the SFR S1CON. In mode B, internal baud rate generator is use to specify the baud rate.
Fig. 9-9: Transmit mode B for Serial 1
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 37 Ver.B SM59R16A2/SM59R08A2 06/2009
SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded
Fig. 9-10: Receive mode B for Serial 1 9.3 Multiprocessor communication of Serial Interface 0 and 1
The feature of receiving 9 bits in Modes 2 and 3 of Serial Interface 0 or in Mode A of Serial Interface 1 can be used for multiprocessor communication. In this case, the slave processors have bit SM20 in S0CON or SM21 in S1CON set to 1. When the master processor outputs slave's address, it sets the Bit 9 to 1, causing a serial port receive interrupt in all the slaves. The slave processors compare the received byte with their network address. If matched, the addressed slave will clear SM20 or SM21 and receive the rest of the message, while other slaves will leave SM20 or SM21 bit unaffected and ignore this message. After addressing the slave, the host will output the rest of the message with the Bit 9 set to 0, so no serial port receive interrupt will be generated in unselected slaves. 9.4 9.4.1 Baud rate generator Serial interface 0 modes 1 and 3
(a) When BRS = 0 (in SFR BRGS):
2SMOD x FOSC Baud Rate = 32 x 12 x (256 - TH1) (b) When BRS = 1 (in SFR BRGS): 2SMOD x FOSC Baud Rate = 64 x 210 - S0REL
(
)
9.4.2
Serial interface 1 modes A and B Baud Rate = FOSC 32 x 2 - S1REL
(
10
)
9.5
Clock source for baud rate
It is not recommended to use the internal OSC as the clock source when the serial interface functions are used. The reason is that the baud rate in the previous section must be as accurate as possible. The internal OSC clock frequency may be varied with +5%. So the user can choose the clock source from external crystal or oscillator.
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 38 Ver.B SM59R16A2/SM59R08A2 06/2009
SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded
10 Watchdog timer The watchdog timer is an 8-bit counter that is incremented once every WDTCLK clock cycles. an external reset, the watchdog timer is disabled and all registers are set to zeros. After
During the initialization period, CPU read the WDTENB and WDTM[3:0] in information block. WDTENB is the disable bit. When this bit is high, the watchdog function will be disabled. The WDTM[3:0] is to set the frequency division for WDTCLK as shown in the figure below. User can to set WDTENB and WDTM[3:0] through the writer.
Fosc 12X 2 WDTM 256 Watchdog reset time = WDTCLK
WDTCLK = Once the watchdog is started it cannot be stopped. User can refreshed the watchdog timer to zero when WDTK register is written by 55h. When Watchdog timer is overflow, the WDTF flag will set to one and automatically reset MCU. WDTF flag can be clear by software or external reset. The
The watchdog timer must be refreshed regularly to prevent reset request signal from becoming active.
Fig. 10-1: Watchdog timer block diagram
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 39 Ver.B SM59R16A2/SM59R08A2 06/2009
SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded
Mnemonic WDTC WDTK
Description Watchdog timer control register Watchdog timer refresh key
Direct
Bit 7 WDTF
Bit 6 Bit 5 Bit 4 Watchdog Timer -
Bit 3 -
Bit 2 -
Bit 1 -
Bit 0 -
RESET 00h 00h
B6h B7h
WDTK[7:0]
Mnemonic: WDTC 7 6 WDTF -
5 -
4 -
3 -
2 -
1 -
Address: B6h 0 Reset 00h
WDTF: Watchdog timer reset flag. When MCU is reset by watchdog, WDTF flag will be set to one by hardware. This flag is cleared by software or external reset.
Mnemonic: WDTK 7 6
5
4 3 WDTK[7:0]
2
1
Address: B7h 0 Reset 00h
WDTK: Watchdog timer refresh key. A programmer must write 0x55 into WDTK register, then the watchdog timer will be cleared to zero.
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 40 Ver.B SM59R16A2/SM59R08A2 06/2009
SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded
11 Interrupt SM59R16A2/SM59R08A2 provides 11 interrupt sources with four priority levels. Each source has its own request flag located in a SFR. Each interrupt requested by the corresponding flag can be enabled or disabled individually by the enable bits in SFR's IEN0, IEN1, and IEN2. When the interrupt occurs, the CPU will vector to the predetermined address as shown in Table 11-1. Once interrupt service has begun, it can be interrupted only by a higher priority interrupt. The interrupt service is terminated by a return from instruction RETI. When an RETI is performed, the processor will return to the instruction that would have been the next instruction when the interrupt occurred. When the interrupt condition occurs, the processor will also indicate this by setting a flag bit. This bit is set regardless of whether the interrupt is enabled or disabled. Each interrupt flag is sampled once per machine cycle, then samples are polled by hardware. If the sample indicates a pending interrupt when the interrupt is enabled, then interrupt request flag is set. On the next instruction cycle, the interrupt will be acknowledged by hardware, forcing an LCALL to appropriate vector address. Interrupt response will require a varying amount of time depending on the state of the processor when the interrupt occurs. If the processor is performing an interrupt service with equal or greater priority, the new interrupt will not be invoked. In the other cases, the response time depends on current instruction. The fastest possible response to an interrupt is 7 machine cycles. This includes one machine cycle for detecting the interrupt and six cycles for perform the LCALL. Table 11-1: Interrupt vectors
Interrupt Request Flags IE0 - External interrupt 0 TF0 - Timer 0 interrupt IE1 - External interrupt 1 TF1 - Timer 1 interrupt RI0/TI0 - Serial channel 0 interrupt TF2/EXF2 - Timer 2 interrupt SPIIF - SPI interrupt ADCIF - A/D converter interrupt EEIIF - Expanded External Interrupt IICIF - IIC interrupt RI1/TI1 - Serial channel 1 interrupt Interrupt Vector Address 0003h 000Bh 0013h 001Bh 0023h 002Bh 004Bh 0053h 005Bh 006Bh 0083h Interrupt Number *(use Keil C Tool) 0 1 2 3 4 5 9 10 11 13 16
*See Keil C about C51 User's Guide about Interrupt Function description
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 41 Ver.B SM59R16A2/SM59R08A2 06/2009
SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded
Mnemonic IEN0 IEN1 IEN2 IP0 IP1
Description Interrupt Enable 0 register Interrupt Enable 1 register Interrupt Enable 2 register Interrupt priority level 0 Interrupt priority level 1
Direct
Bit 7 EA EXEN2 -
Bit 6 -
Bit 5 Interrupt ET2 IEIIC IP0.5 IP1.5
Bit 4 ES0 IP0.4 IP1.4
Bit 3 ET1 IEEEI IP0.3 IP1.3
Bit 2 EX1 IEADC IP0.2 IP1.2
Bit 1 ET0 IESPI IP0.1 IP1.1
Bit 0 EX0 ES1 IP0.0 IP1.0
RESET 00h 00h 00h 00h 00h
A8h B8h 9Ah A9h B9h
-
Interrupt Enable 0 register(IEN0)
Mnemonic: IEN0 7 6 EA 5 ET2 4 ES0 3 ET1 2 EX1 1 ET0 Address: A8h 0 Reset EX0 00h
EA: EA = 0 : disable all interrupt. EA = 1 : enable all interrupt. ET2: ET2 = 0 : disable Timer 2 overflow or external reload interrupt. ES0: ES0 = 0 : disable Serial channel 0 interrupt. ET1: ET1 = 0 : disable Timer 1 overflow interrupt. EX1: EX1 = 0 : disable external interrupt 1. ET0: ET0 = 0 : disable Timer 0 overflow interrupt. EX0: EX0 = 0 : disable external interrupt 0.
Interrupt Enable 1 register(IEN1)
Mnemonic: IEN1 7 6 EXEN2 5 IEIIC 4 3 IEEEI 2 IEADC 1 IESPI Address: B8h 0 Reset 00h
EXEN2: Timer 2 reload interrupt enable EXEN2 = 0 : disable Timer 2 external reload interrupt. IEIIC: IIC interrupt enable. IEIICS = 0 : disable IIC interrupt. IEEEI: EEI interrupt enable IEEEI = 0 : disable EEI interrupt IEADC : A/D converter interrupt enable IEADC = 0 : disable ADC interrupt. IESPI: SPI interrupt enable. IESPI = 0 : disable SPI interrupt.
Interrupt Enable 2 register(IEN2)
Mnemonic: IE2 7 6 5 4 3 2 1 Address: 9Ah 0 Reset ES1 00h
ES1: ES1=0 - Disable Serial channel 1 interrupt. Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 42 Ver.B SM59R16A2/SM59R08A2 06/2009
SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded
Interrupt request register(IRCON)
Mnemonic: IRCON 7 6 5 EXF2 TF2 IICIF 4 3 EEIIF 2 ADCIF 1 SPIIF Address: C0h 0 Reset 00h
EXF2: Timer 2 external reload flag, must be cleared by software. TF2: Timer 2 overflow flag, must be cleared by software. IICIF: IIC interrupt flag must be cleared after the RxIF and TxIF at IICS register clear by software EEIIF: EEI interrupt flag, must be cleared by software. ADCIF: A/D converter interrupt flag, must be cleared by software SPIIF: SPI interrupt flag, must be cleared by software.
11.1 Priority level structure All interrupt sources are combined in groups: Table 11-2: Priority level groups
External interrupt 0 Timer 0 interrupt External interrupt 1 Timer 1 interrupt Serial channel 0 interrupt Timer 2 interrupt Groups Serial channel 1 interrupt SPI interrupt ADC interrupt EEI interrupt IIC interrupt
Each group of interrupt sources can be programmed individually to one of the four priority levels by setting or clearing one bit in the SFRs IP0 and IP1. If requests of the same priority level is received simultaneously, an internal polling sequence determines which request is serviced first.
Mnemonic: IP0 7 6 Mnemonic: IP1 7 6 5 IP0.5 4 IP0.4 3 IP0.3 2 IP0.2 1 IP0.1 Address: A9h 0 Reset IP0.0 00h Address: B9h 0 Reset IP1.0 00h
5 IP1.5
4 IP1.4
3 IP1.3
2 IP1.2
1 IP1.1
Table 11-3: Priority levels
IP1.x 0 0 1 1 IP0.x 0 1 0 1 Priority Level Level0 (lowest) Level1 Level2 Level3 (highest)
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 43 Ver.B SM59R16A2/SM59R08A2 06/2009
SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded
Table 11-4: Groups of priority
Bit IP1.0, IP0.0 IP1.1, IP0.1 IP1.2, IP0.2 IP1.3, IP0.3 IP1.4, IP0.4 IP1.5, IP0.5 External interrupt 0 Timer 0 interrupt External interrupt 1 Timer 1 interrupt Serial channel 0 interrupt Timer 2 interrupt Group Serial channel 1 interrupt SPI interrupt ADC interrupt EEI interrupt IIC interrupt
Table 11-5: Polling sequence
Interrupt source External interrupt 0 Serial channel 1 interrupt Timer 0 interrupt SPI interrupt External interrupt 1 ADC interrupt Timer 1 interrupt EEI interrupt Serial channel 0 interrupt Timer 2 interrupt IIC interrupt Sequence
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 44 Ver.B SM59R16A2/SM59R08A2 06/2009
Polling sequence
SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded
12 Power Management Unit Power management unit serves two power management modes, IDLE and STOP, for the users to do power saving function.
Mnemonic: PCON 7 6 SMOD MDUF 5 4 PMW 3 2 1 STOP Address: 87h 0 Reset IDLE 00h
STOP: Stop mode control bit. Setting this bit turning on the Stop Mode. Stop bit is always read as 0 IDLE: Idle mode control bit. Setting this bit turning on the Idle Mode. Idle bit is always read as 0
12.1 12.1
Idle mode
Setting the IDLE bit of PCON register invokes the IDLE mode. The IDLE mode stop the clock source for CPU but keep the peripherals under running condition. The power consumption will drop because the CPU is not active now. The CPU can exit the IDLE state with any interrupts or a reset. 12.2 12.2 Stop mode
Setting the STOP bit of PCON register invokes the STOP mode. All internal clocking in this mode is turned off. The CPU will exit this state from a no-clocked external interrupt or a reset condition. Internally generated interrupts (timer, serial port, watchdog ...) are not useful since they require clocking activity.
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 45 Ver.B SM59R16A2/SM59R08A2 06/2009
SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded
13 Pulse Width Modulation (PWM) SM59R16A2/SM59R08A2 provides four-channel PWM outputs. The 4 channels can be used simultaneously. But their configuration (the counting bit number and counting frequency) will be the same defined in one SFR.
Mnemonic PWMC PWMD0H PWMD0L PWMD1H PWMD1L PWMD2H PWMD2L PWMD3H PWMD3L Description PWM Control register PWM 0 Data register high byte PWM 0 Data register low byte PWM 1 Data register high byte PWM 1 Data register low byte PWM 2 Data register high byte PWM 2 Data register low byte PWM 3 Data register high byte PWM 3 Data register low byte
Direct
Bit 7 -
Bit 6 -
Bit 5 PWM
Bit 4
Bit 3 PWM3 EN
Bit 2 PWM2 EN
Bit 1 PWM1 EN
Bit 0 PWM0 EN
RESET 00h 00h 00h
B5h BCh BDh BEh BFh B1h B2h B3h B4h
PWMM[1:0] -
PWMD0[11:8]
PWMD0[7:0] PWMD1[7:0] PWMD2[7:0] PWMD3[7:0] Address: B5h 0 Reset PWM0EN 00h PWMD3[11:8] PWMD2[11:8] PWMD1[11:8]
00h 00h 00h 00h 00h 00h
Mnemonic: PWMC 7 6 5 4 PWMM[1:0]
3 PWM3EN
2 PWM2EN
1 PWM1EN
PWMM[1:0 PWM mode select. ]: When PWMM[1:0] = 00 or 11 , the PWM output frequency = Fosc/256. When PWMM[1:0] = 01 , the PWM output frequency = Fosc/1024. When PWMM[1:0] = 10 , the PWM output frequency = Fosc/4096. Also PWMM[1:0] Mode 00 8-bit mode 01 10-bit mode 10 12-bit mode 11 8-bit mode here Fosc is the external crystal or oscillator frequency PWM3EN: PWM Channel 3 enable control bit. PWM3EN = 1 - PWM Channel 3 enable. PWM3EN = 0 - PWM Channel 3 disable. PWM2EN: PWM Channel 2 enable control bit. PWM2EN = 1 - PWM Channel 2 enable. PWM2EN = 0 - PWM Channel 2 disable. PWM1EN: PWM Channel 1 enable control bit. PWM1EN = 1 - PWM Channel 1 enable. PWM1EN = 0 - PWM Channel 1 disable. PWM0EN: PWM 0 Channel 0 enable control bit. PWM0EN = 1 - PWM Channel 0 enable. PWM0EN = 0 - PWM Channel 0 disable. Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 46 Ver.B SM59R16A2/SM59R08A2 06/2009
SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded
Mnemonic: PWMD0H 7 6 5 Mnemonic: PWMD0L 7 6 5
4 -
3
2 1 PWMD0[11:8]
Address: BCh 0 Reset 00h Address: BDh 0 Reset 00h
4 3 PWMD0[7:0]
2
1
PWMD0[11:0]: PWM channel 0 data register. Mnemonic: PWMD1H 7 6 5 Mnemonic: PWMD1L 7 6 5 Address: BEh 0 Reset 00h Address: BFh 0 Reset 00h
4 -
3
2 1 PWMD1[11:8]
4 3 PWMD1[7:0]
2
1
PWMD1[11:0]: PWM channel 1 data register. Mnemonic: PWMD2H 7 6 5 Mnemonic: PWMD2L 7 6 5 Address: B1h 0 Reset 00h Address: B2h 0 Reset 00h
4 -
3
2 1 PWMD2[11:8]
4 3 PWMD2[7:0]
2
1
PWMD2[11:0]: PWM channel 2 data register. Mnemonic: PWMD3H 7 6 5 Mnemonic: PWMD3L 7 6 5 Address: B3h 0 Reset 00h Address: B4h 0 Reset 00h
4 -
3
2 1 PWMD3[11:8]
4 3 PWMD3[7:0]
2
1
PWMD3[11:0]: PWM channel 3 data register.
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 47 Ver.B SM59R16A2/SM59R08A2 06/2009
SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded
14 IIC function As most of the IIC we have been familiar with, this IIC module uses the SCL (clock) and the SDA (data) line to communicate with the other IIC interfaces. Its speed can be selected up to 400Kbps (maximum) by software setting the SFR IICBR[2:0]. The IIC module can be either master or slave, provided two interrupts (RXIF, TXIF), and has two addresses for data transmission. It will generate START, repeated START and STOP signals automatically in master mode and can detects START, repeated START and STOP signals in slave mode. The maximum communication length and the number of devices that can be connected are limited by a maximum bus capacitance of 400pF. SM59R16A2/SM59R08A2 IIC function is fully compatible to most of the other chips'. So there is no barrier in the mutual communication.
Mnemonic IICCTL IICS IICA1 IICA2 IICRWD Description IIC control register IIC status register IIC Address 1 register IIC Address 2 register IIC Read/Write register
Direct
Bit 7 IICEN MStart
Bit 6 Bit 5 Bit 4 IIC function BF RXIF MSS TXIF MAS RDR IICA1[7:1] IICA2[7:1]
Bit 3 RStart TDR
Bit 2
Bit 1 IICBR[2:0]
Bit 0
RESET 04h 00h A0h 60h 00h
F9h F8h FAh FBh FCh
RXAK
TXAK
RW MATCH1 or RW1 MATCH2 or RW2
IICSRWD[7:0] Address: F9h 0 Reset 04h
Mnemonic: IICCTL 7 6 5 IICEN BF MSS
4 MAS
3 RStart
2
1 IICBR[2:0]
IICEN: Enable IIC module IICEN = 1 is Enable IICEN = 0 is Disable. BF: Bus failed flag (used in master mode only) When the module is transmitting a "1" to SDA line but detected as a "0" from SDA line in master mode, it is called as arbitration loss. This bit can be cleared by software. MSS: Master or slave mode select. MSS = 1 is master mode. MSS = 0 is slave mode. *The software must set this bit before setting others register. MAS: Master address select (master mode only) MAS = 0 is to use IICA1. MAS = 1 is to use IICA2. RStart: Re-start control bit (master mode only) When this bit is set, the module will generate a start condition to the SDA and SCL lines (after current ACK) and send out the calling address which is stored in either IICA1 or IICA2 (selected by MAS control bit). After the address is sent out, this bit will be cleared by hardware.
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 48 Ver.B SM59R16A2/SM59R08A2 06/2009
SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded IICBR[2:0]: Baud rate selection (master mode only), where Fosc is the external crystal or oscillator frequency. The default is Fosc/512 for users' convenience. IICBR[2:0] Baud rate 000 Fosc/32 001 Fosc/64 010 Fosc/128 011 Fosc/256 100 Fosc/512 101 Fosc/1024 110 Fosc/2048 111 Fosc/4096 Mnemonic: IICS 7 6 MStart RxIF Address: F8h 0 Reset RW 00h
5 TxIF
4 RDR
3 TDR
2 RxAK
1 TxAK
MStart: Master start control bit (master mode only) If this bit is set, the module will generate a start condition to the SDA and SCL lines, and send out the calling address which is stored in either IICA1 or IICA2 (selected by MAS control bit). After software clears this bit, the module will generate a stop condition to the SDA and SCL. RxIF: Data receive interrupt flag It is set after the IICRWD (IIC read /write data buffer) is loaded with a newly receive data. After software clears this bit, the IICIFIIC interrupt flagwill cleared. TxIF: Data transmit interrupt flag It is set when all the 8 bits in the shift register are transmitted, the 8 bits are from IICRWD (IIC read /write data buffer) downloaded into the shift register. After software clears this bit, the IICIF IIC interrupt flagwill cleared. RDR: Read data ready It is set to high by hardware when a new byte is received and stored in IICRWD. The software must clear this bit after it gets the data from IICRWD. The IIC module is able to write new data into IICRWD only when this bit is cleared. TDR: Transmit data ready After putting the data into IICRWD in transmission, the software needs to set this bit to `1' to inform the IIC module to send the data out. After IIC module finishes sending the data from IICRWD, this bit will be cleared automatically. RxAK: Receive acknowledgement This is a read-only bit judged by the transmitting side only. If the IIC module is in the master mode : after it transmits the 8-bit data to the slave side, the slave side will returned RxAK = 0 : the slave receives the data successfully = 1 : the slave fails to receive the data If the IIC module is in the slave mode : after it sends the 8-bit data to the master side, the master side will returned RxAK = 0 : the master receives the data successfully(in some application, it may be that the master wants more data) = 1 : the master fails to receive the data (in some applications, it may be that the master does not want any more data) TxAK: Transmit acknowledgement It is the corresponding bit of RxAK in the receiving side. It represents the receiving status as explained in RxAK. Actually, it is sent as the 9th bit in one byte transmission as show in Fig. 14-1. RW: Slave mode read or write It is a read-only bit used in slave mode only. It is from Bit 0 of IICA1 or IICA2 of the master side as described below = 0 : master asks this IIC module (in slave mode) to receive data (read) =1 : master asks this IIC module (in slave mode) to transmit data (write) Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 49 Ver.B SM59R16A2/SM59R08A2 06/2009
SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded
Fig. 14-1: Acknowledgement bit in the 9th bit of a byte transmission
Mnemonic: IICA1 7 6 5 Address: FAh 0 Reset Match1 or RW1 A0h
4 3 IICA1[7:1]
2
1
Slave mode: IICA1[7:1]: IIC Address registers This is the first 7-bit address for this slave module. It will be checked when an address (from master) is received Match1: When IICA1 matches with the received address from the master side, this bit will set to 1 by hardware. When IIC bus is stopped, this bit will clear automatically. Master mode: IICA1[7:1]: IIC Address registers This 7-bit address indicate the slave with which it want to communicate. RW1: This bit will be sent out as RW of the slave side if the module has set the MStart or RStart bit. It appears at the 8th bit after the IIC address as shown in Fig. 14-2. It is used to tell the salve the direction of the following communication. If it is 1, the module is in master receive mode. If 0, the module is in master transmit mode.
Fig. 14-2: RW bit in the 8th bit after IIC address
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 50 Ver.B SM59R16A2/SM59R08A2 06/2009
SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded
Mnemonic: IICA2 7 6 5
4 IICA2[7:1] R/W
3
2
1
Address: FBh 0 Reset Match2 or RW2 60h R or R/W
Slave mode: IICA2[7:1]: IIC Address registers This is the second 7-bit address for this slave module. It will be checked when an address (from master) is received Match2: When IICA2 matches with the received address from the master side, this bit will set to 1 by hardware. When IIC bus is stopped, this bit will clear automatically. Master mode: IICA2[7:1]: IIC Address registers This 7-bit address indicate the slave with which it want to communicate. RW2: This bit will be sent out as RW of the slave side if the module has set the MStart or RStart bit. It is used to tell the salve the direction of the following communication. If it is 1, the module is in master receive mode. If 0, the module is in master transmit mode. Mnemonic: IICRWD 7 6 5 Address: FCh 0 Reset 00h
4 3 IICRWD[7:0]
2
1
IICRWD[7:0]: IIC read write data buffer. In receiving (read) mode, the received byte is stored here. In transmitting mode, the byte to be shifted out through SDA stays here.
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 51 Ver.B SM59R16A2/SM59R08A2 06/2009
SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded
15 SPI function Serial Peripheral Interface (SPI) is a synchronous protocol that allows a master device to initiate communication with slave devices. There are 4 signals used in SPI, they are SPI_MOSI: data output in the master mode, data input in the slave mode, SPI_MISO: data input in the master mode, data output in the master mode, SPI_SCK: clock output form the master, the above data are synchronous to this signal SPI_SS: input in the slave mode. This slave device detects this signal to judge if it is selected by the master. In the master mode, it can select the desired slave device by any IO with value = 0. Fig. 15-1 is an example showing the relation of the 4 signals between master and slaves. Master
MOSI MISO CLK IO IO
Slave 1
MOSI MISO CLK SS
Slave 2
MOSI MISO CLK SS
Fig. 15-1: SPI signals between master and slave devices There is only one channel SPI interface. The SPI SFRs are shown as below:
SPI SPIC1 SPIC2 SPIS SPITXD SPIRXD Description
SPI control register 1 SPI control register 2
Direct
Bit 7
SPIEN
Bit 6
SPIMSS SPIMLS
Bit 5
SPISSP
Bit 4
SPICKP SPITXIF
Bit 3
SPICKE
Bit 2
Bit 1
SPIBR[2:0]
Bit 0
RESE T 08h 00h 40h 00h 00h
SPI function F1h F2h F5h F3h F4h SPIFD TBC[2:0]
SPIOV
SPITDR SPIRXIF
RBC[2:0]
SPIRDR SPIRS
SPI status register SPI transmit data buffer SPI receive data buffer
SPITXD[7:0] SPIRXD[7:0]
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 52 Ver.B SM59R16A2/SM59R08A2 06/2009
SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded
Mnemonic: SPIC1 7 6 5 SPIEN SPIMSS SPISSP
4
SPICKP
Address: F1h 3 2 1 0 SPICKE SPIBR[2:0]
Reset 08h
SPIEN: Enable SPI module. "1" is Enable. "0" is Disable. SPIMSS: Master or Slave mode Select "1" is Master mode. "0" is Slave mode. SPISSP: Slave Select (SS) active polarity (slave mode used only) "1" - high active. "0" - low active. SPICKP: Clock idle polarity (master mode used only) "1" - SCK high during idle. Ex :
"0" - SCK low during idle. Ex :
SPICKE: Clock sample edge select. "1" - data latch in rising edge "0" - data latch in falling edge. * To ensure the data latch stability, SM59R16A2/SM59R08A2 generate the output data as given in the following example, the other side can latch the stable data no matter in rising or falling edge.
sufficient set-up time
sufficient hold time
SPIBR[2:0]: SPI baud rate select (master mode used only), here Fosc is the external crystal or oscillator frequency : SPIBR[2:0] Baud rate 0:0:0 Fosc/4 0:0:1 Fosc/8 0:1:0 Fosc/16 0:1:1 Fosc/32 1:0:0 Fosc/64 1:0:1 Fosc/128 1:1:0 Fosc/256 1:1:1 Fosc/512
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 53 Ver.B SM59R16A2/SM59R08A2 06/2009
SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded
Mnemonic: SPIC2 7 6 5 SPIFD TBC[2:0]
4
3 -
2
1 RBC[2:0]
Address: F2h 0 Reset 00h
SPIFD: Full-duplex mode enable. "1" : enable full-duplex mode. "0" : disable full-duplex mode. When it is set, the TBC[2:0] and RBC[2:0] will be reset and keep to zero, i.e., only 8-bit communication is allowed in the full-duplex mode. When the master device transmits data to the slave device via the MOSI line, the slave device responds sends data back to the master device via the MISO line. This implies that full-duplex transmission with both out-data and in-data are synchronized with the same clock SCK as shown below.
Input Shift register SPIRXD
MISO
MISO
Output Shift register SPITXD
Output Shift register SPITXD
MOSI
MOSI
Input Shift register SPIRXD
Clock Generator
SCK
SCK
SyncMos Master
SyncMos Slave
TBC[2:0]: SPI transmitter bit counter, here 1-8 bits are allowed except for the full-duplex mode TBC[2:0] Bit counter 0:0:0 8 bits output 0:0:1 1 bit output 0:1:0 2 bits output 0:1:1 3 bits output 1:0:0 4 bits output 1:0:1 5 bits output 1:1:0 6 bits output 1:1:1 7 bits output RBC[2:0]: SPI receiver bit counter, here 1-8 bits are allowed except for the full-duplex mode RBC[2:0] Bit counter 0:0:0 8 bits input 0:0:1 1 bit input 0:1:0 2 bits input 0:1:1 3 bits input 1:0:0 4 bits input 1:0:1 5 bits input 1:1:0 6 bits input 1:1:1 7 bits input
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 54 Ver.B SM59R16A2/SM59R08A2 06/2009
SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded
Mnemonic: SPIS 7 6 5 SPIMLS SPIOV
4 SPITXIF
3 SPITDR
2 SPIRXIF
1 SPIRDR
Address: F5h 0 Reset SPIRS 40h
SPIMLS: MSB or LSB output /input first "1" : MSB output/input first "0" : LSB output/input first SPIOV: Overflow flag. When SPIRDR is set (one byte in SPIRXD but has not been taken away) and the next data also enters (there is no blocking function), this flag will be set to inform that the received data in SPIRXD is damaged by this overflow. It is clear by hardware when SPIRDR is cleared. SPITXIF: Transmit Interrupt Flag. This bit is set when the data of the SPITXD register is downloaded to the shift register. SPITDR: Transmit Data Ready. When MCU finish writing data to SPITXD register, the MCU needs to set this bit to `1' to inform the SPI module to send the data. After SPI module finishes sending the data from SPITXD or SPITXD is downloaded to shift register, this bit will be cleared automatically. SPIRXIF: Receive Interrupt Flag. This bit is set after the SPIRXD is loaded with a newly receive data. SPIRDR: Receive Data Ready. When a byte is received, SPIRDR is set as a flag to inform MCU. The MCU must clear this bit after it gets the data from SPIRXD register. If the SPI module on the transmit side writes new data into the SPIRXD before this bit is cleared, then the data will be overwritten. SPIRS: Receive Start. This bit set to "1" to inform the SPI module to receive the data into SPIRXD register. Mnemonic: SPITXD 7 6 5 Address: F3h Reset 00h
4 3 SPITXD[7:0]
2
1
0
SPITXD[7:0]: Transmit data buffer. Mnemonic: SPIRXD 7 6 5 Address: F4h 0 Reset 00h
4 3 SPIRXD[7:0]
2
1
SPIRXD[7:0]: Receive data buffer.
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 55 Ver.B SM59R16A2/SM59R08A2 06/2009
SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded
16 Expanded External Interrupt (EEI) interface Expanded External Interrupt (EEI) interface can be connected to an 8 x n matrix keyboard or any similar devices.It has 8 inputs with programmable interrupt capability on either high or low level.These 8 inputs are through P1 and can be the external interrupts to leave from the idle and stop modes.The 8 inputs are independent from each other but share the same interrupt vector.
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 IEEEI: EEI interrupt enable
OR
EEIIF: EEI interrupt
Fig. 16-1: Interrupts from EEI 8 inputs
EEI KBLS KBE KBF
Description EEI level selection EEI input enable EEI flag
Direct 93h 94h 95h
Bit 7 KBLS7 KBE7 KBF7
Bit 6 Bit 5 Bit 4 EEI function KBLS6 KBLS5 KBLS4 KBE6 KBE5 KBE4 KBF6 KBF5 KBF4
Bit 3 KBLS3 KBE3 KBF3
Bit 2 KBLS2 KBE2 KBF2
Bit 1 KBLS1 KBE1 KBF1
Bit 0 KBLS0 KBE0 KBF0
RESET 00h 00h 00h
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 56 Ver.B SM59R16A2/SM59R08A2 06/2009
SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded Mnemonic: KBLS 7 6 KBLS.7 KBLS.6 Address: 93h 0 Reset KBLS.0 00h
5 KBLS.5
4 KBLS.4
3 KBLS.3
2 KBLS.2
1 KBLS.1
KBLS.7: EEI line 7 level selection bit 0 : enable a low level detection on P17. 1 : enable a high level detection on P17. KBLS.6: EEI line 6 level selection bit 0 : enable a low level detection on P16. 1 : enable a high level detection on P16. KBLS.5: EEI line 5 level selection bit 0 : enable a low level detection on P15. 1 : enable a high level detection on P15. KBLS.4: EEI line 4 level selection bit 0 : enable a low level detection on P14. 1 : enable a high level detection on P14. KBLS.3: EEI line 3 level selection bit 0 : enable a low level detection on P13. 1 : enable a high level detection on P13. KBLS.2: EEI line 2 level selection bit 0 : enable a low level detection on P12. 1 : enable a high level detection on P12. KBLS.1: EEI line 1 level selection bit 0 : enable a low level detection on P11. 1 : enable a high level detection on P11. KBLS.0: EEI line 0 level selection bit 0 : enable a low level detection on P10. 1 : enable a high level detection on P10. Mnemonic: KBE 7 6 KBE.7 KBE.6 Address: 94h 0 Reset KBE.0 00h
5 KBE.5
4 KBE.4
3 KBE.3
2 KBE.2
1 KBE.1
KBE.7: EEI line 7 enable bit 0 : enable standard I/O pin. 1 : enable KBF.7 bit in KBF register to generate an interrupt request. KBE.6: EEI line 6 enable bit 0 : enable standard I/O pin. 1 : enable KBF.6 bit in KBF register to generate an interrupt request. KBE.5: EEI line 5 enable bit 0 : enable standard I/O pin. 1 : enable KBF.5 bit in KBF register to generate an interrupt request. KBE.4: EEI line 4 enable bit 0 : enable standard I/O pin. 1 : enable KBF.4 bit in KBF register to generate an interrupt request. KBE.3: EEI line 3 enable bit 0 : enable standard I/O pin. 1 : enable KBF.3 bit in KBF register to generate an interrupt request. KBE.2: EEI line 2 enable bit 0 : enable standard I/O pin. 1 : enable KBF.2 bit in KBF register to generate an interrupt request. KBE.1: EEI line 1 enable bit 0 : enable standard I/O pin. 1 : enable KBF.1 bit in KBF register to generate an interrupt request. KBE.0: EEI line 0 enable bit 0 : enable standard I/O pin. 1 : enable KBF.0 bit in KBF register to generate an interrupt request. Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 57 Ver.B SM59R16A2/SM59R08A2 06/2009
SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded
Mnemonic: KBF 7 6 KBF.7 KBF.6
5 KBF.5
4 KBF.4
3 KBF.3
2 KBF.2
1 KBF.1
Address: 95h 0 Reset KBF.0 00h
KBF.7: EEI line 7 flag This is set by hardware when P17 detects a programmed level. It generates a EEI interrupt request if KBE.7 is also set. It must be cleared by software. KBF.6: EEI line 6 flag This is set by hardware when P16 detects a programmed level. It generates a EEI interrupt request if KBE.6 is also set. It must be cleared by software. KBF.5: EEI line 5 flag This is set by hardware when P15 detects a programmed level. It generates a EEI interrupt request if KBE.5 is also set. It must be cleared by software. KBF.4: EEI line 4 flag This is set by hardware when P14 detects a programmed level. It generates a EEI interrupt request if KBE.4 is also set. It must be cleared by software. KBF.3: EEI line 3 flag This is set by hardware when P13 detects a programmed level. It generates a EEI interrupt request if KBE.3 is also set. It must be cleared by software. KBF.2: EEI line 2 flag This is set by hardware when P12 detects a programmed level. It generates a EEI interrupt request if KBE.2 is also set. It must be cleared by software. KBF.1: EEI line 1 flag This is set by hardware when P11 detects a programmed level. It generates a EEI interrupt request if KBE.1 is also set. It must be cleared by software. KBF.0: EEI line 0 flag This is set by hardware when P10 detects a programmed level. It generates a EEI interrupt request if KBE.0 is also set. It must be cleared by software.
P1.x
KBFx
KBLSx Fig. 16-2: Block diagram of EEI input
KBEx
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 58 Ver.B SM59R16A2/SM59R08A2 06/2009
SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded
17 EEPROM For any byte in the 64KB/32KB Flash memory which is not programmed, it can be used to record the data. The data can be stored and updated as if there is EEPROM embedded. Since it is not really saved into EEPROM, it is also called "virtual EEPROM" function. The EEPROM function in SM59R16A2/SM59R08A2 is easy to be used. Basically, it is done by hardware circuits to reduce the efforts in firmware coding. The necessary data move, page erase and write back, etc, are executed automatically by this hardware. It is worth reminding again that the location of the EEPROM can be any byte within the program Flash where no program code occupies. Users must be very careful in doing EEPROM write, not to write to the program area. The users can only set the PMW (program memory write) bit to do the EEPROM function through ACC register. If PMW = 1, the MOVX instruction will read/write the data from/to the Flash memory directly, instead of the internal or external SRAM. Data overwrite (update) is also supported because the hardware circuits will erase the original data first, then write the new data.
Mnemonic PCON PES Description Power Control Program Memory Page Erase Control Register
Direct
Bit 7 SMOD EPE
87h A1h
Bit 6 Bit 5 Bit 4 EEPROM Function MDUF PMW -
Bit 3 -
Bit 2 -
Bit 1 STOP -
Bit 0 IDLE -
RESET 00h 00h
Mnemonic: PCON 7 6 SMOD MDUF
5 -
4 PMW
3 -
2 -
1 STOP
Address: 87h 0 Reset IDLE 00h
When the PMW is cleared or after reset, the MOVX instructions allow read/write access to the data memory address space again. The software switches the PMW bit to enable access to the program memory address space. The following table shows the program memory instructions when the PMW bit is set.
Mnemonic MOVX A,@Ri MOVX A,@DPTR MOVX @Ri,A MOVX @DPTR,A Mnemonic: PES 7 6 EPE Description Move program memory data (8-bits addr.) to ACC Move program memory data (16-bits addr.) to ACC Move ACC to program memory (8-bits addr.) Move ACC to program memory (16-bits addr.) Address: A1h 0 Reset 00h
5 -
4 -
3 -
2 -
1 -
When enable the EPE bitthe Page Erase Each page include 512 bytes function can be executed by below Instructions
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 59 Ver.B SM59R16A2/SM59R08A2 06/2009
SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded
ORL MOV MOV MOV MOVX MOV ANL
PCON,#010h DPTR,#0200h PES,#080h A,#0FFH @DPTR,A PES,#00h PCON,#0EFh
; ; ; ; ; ; ; ;
Enable Program Memory read/write Define page erase area from 0x0200 to 0x03FF Enable Page erase function Put 0xFF into ACC register When this instruction executeThe Program Memory 0x0200 to 0X03FF value will all change to 0xFF Disable Page erase function Disable Program Memory read/write
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 60 Ver.B SM59R16A2/SM59R08A2 06/2009
SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded
18 10-bit Analog-to-Digital Converter (ADC) SM59R16A2/SM59R08A2 provides four channel 10-bit ADC. This ADC is in SAR architecture with excellent precision. It is advised that there will be no large current surge caused by IO ports or any other functions when the ADC is measuring. The large current surge may influence the voltage reference, and make the results inaccurate. The Digital output of the sampled analog signal is put into ADCD [9:0]. The ADC interrupt vector is 53h. The embedded 4-channel ADC is a 10-bit-resolution device with measurement range 0 ~ 3.3V. The 4 channels are in Port4 [7] ~ Port4 [4]. The following figure shows the precision of this ADC in real application:
P.S. When ADC module used at VDD=5.0V systemUser must attention below two items 1. The Port474must output "0000" value to delete the offset voltage before start the ADC convertor 2.
Fig. 20-1: The precision of 10-b ADCThe VDD=3.3V
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 61 Ver.B SM59R16A2/SM59R08A2 06/2009
SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded Mnemonic ADCC1 ADCC2 ADCDH ADCDL Description ADC Control 1 ADC Control 2 ADC data high byte ADC data low byte
Direct
Bit 7 COM
Bit 6 START
ABh ACh ADh AEh
Bit 5 ADC ADC8B -
Bit 4 -
Bit 3
Bit 2
Bit 1
Bit 0
RESET 00h 00h 00h 00h
ADC3E ADC2E ADCCH[1:0]
ADC1E ADC0E ADCCS[1:0] ADCDH [1:0]
ADCDL[7:0] Address: ABh 0 Reset ADC0E 00h
Mnemonic: ADCC1 7 6 -
5 -
4 -
3 ADC3E
2 ADC2E
1 ADC1E
ADC3E: =0 : No external analog input data can be accepted via ADC Chanel 3 =1 : ADC Channel 3 is enable, analog input data can be read through it. ADC2E: =0 : No external analog input data can be accepted via ADC Chanel 2 =1 : ADC Channel 2 is enable, analog input data can be read through it. ADC1E: =0 : No external analog input data can be accepted via ADC Chanel 1 =1 : ADC Channel 1 is enable, analog input data can be read through it. ADC0E: =0 : No external analog input data can be accepted via ADC Chanel 0 =1 : ADC Channel 0 is enable, analog input data can be read through it. Mnemonic: ADCC2 7 6 COM START 5 ADC8B 4 3 2 ADCCH[1:0] Address: ACh 1 0 Reset ADCCS[1:0] 00h
COM: When one conversion is done, COM will be set to 1 to notify the users. It will be clear automatically by hardware. This bit is read only. START: When this bit is set, the ADC will be start conversion. It will be clear automatically by hardware. ADC8B: Select 10-bit or 8-bit of ADC converted data. = 0: (default value) 10-bit data conversion ADCD[9:0], where ADCD [9:8] = ADCDH [1:0] and ADCD [7:0] = ADCDL [7:0] = 1: 8-bit data conversion ADCD[7:0] = ADCDL [7:0] ADCCH[1:0] The analog input signal can be chosen with it : = 00 : Chanel 0 is used as input = 01 : Chanel 1 is used as input = 10 : Chanel 2 is used as input = 11 : Chanel 3 is used as input The users must also set the corresponding channel enable bit to 1 as described in ADCC1. ADCCS[1:0]: This is used to select the clock frequency fed to the ADC module : = 00 : ADC clock is system clock divided by 8 = 01 : ADC clock is system clock divided by 16 = 10 : ADC clock is system clock divided by 32 = 11 : ADC clock is system clock divided by 64 Since ADC takes about 20 ADC clock to finish one conversion, so the fastest speed of one conversion is about 160 system clocks with ADCLK=00 ADC Clock =
Fclk 8 x 2 ADCCS
20 ADC Clock 1 ADC Sample Rate = ADC Conversion Time
ADC Conversion Time =
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 62 Ver.B SM59R16A2/SM59R08A2 06/2009
SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded
*The ADC clock (Fclk/n) maximum 500KHz.
ADCCS[1:0] 00 01 10 11 Mnemonic: ADCDH 7 6 Fclk/8 Fclk/16 Fclk/32 Fclk/64 ADC clock (Fclk: 1MHz ~ 4MHz) (Fclk: 4MHz ~ 8MHz) (Fclk: 8MHz ~ 16MHz) (Fclk: 16MHz ~ 32MHz) Address: ADh 1 0 Reset ADCDH[1:0] 00h
5
4
3
2
ADCDH[1:0]: The high bits of digital output of this ADC Mnemonic: ADCDL 7 6 5 4 3 ADCDL[7:0] 2 1 Address: AEh 0 Reset 00h
ADCDL[7:0]: The low bits of digital output of this ADC
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 63 Ver.B SM59R16A2/SM59R08A2 06/2009
SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded
Operating Conditions
Symbol TA VDD33 VDD5 Description Operating temperature Supply voltage Supply voltage Min. -40 2.7 4.5 Typ. 25 3.3 5.0 Max. 85 3.6 5.5 Unit. V V Remarks Ambient temperature under bias
DC Characteristics
(TA = -40 degree C to 85 degree C, Vdd = 3.3V) Symbol VIL1 VIL2 VIH1 VIH2 VOL1 VOL2 VOH1 VOH2 IIL ITL ILI R RES C IO I CC Parameter Input Low Voltage Input Low Voltage Input High Voltage Input High Voltage Output Low Voltage Output Low Voltage Output High Voltage Output High Voltage Logical 0 Input Current Logical Transition Current Input Leakage Current Reset Pull-down Resistance Pin Capacitance Power Supply Current Valid port 0,1,2,3,4,5 RES, XTAL1 port 0,1,2,3,4,5 RES, XTAL1 port 0, ALE port 1,2,3,4,5 port 0 port 1,2,3,4,5,ALE port 1,2,3,4,5 port 1,2,3,4,5 port 0 RES Vdd 50 Min. -0.5 0 2.0 70%Vdd Max. 0.8 0.8 Vdd+0.5 Vdd+0.5 0.45 0.45 Unit V V V V V V V V V V uA uA uA Kohm pF mA mA uA Freq=1MHz, Ta=25 Active mode, 16MHz Idle mode, 16MHz Power down mode Test Conditions Vdd=3.3V
2.4 90%Vdd 2.4 90%Vdd -75 -650 10 300 10 25 20 30
IOL=3.2mA IOL=1.6mA IOH=-800uA IOH=-80uA IOH=-60uA IOH=-10uA Vin=0.45V Vin=2.0V 0.45VSpecifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 64 Ver.B SM59R16A2/SM59R08A2 06/2009
SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded (TA = -40 degree C to 85 degree C, Vdd = 5.0V) Symbol VIL1 VIL2 VIH1 VIH2 VOL1 VOL2 VOH1 VOH2 IIL ITL ILI R RES C IO I CC Parameter Input Low Voltage Input Low Voltage Input High Voltage Input High Voltage Output Low Voltage Output Low Voltage Output High Voltage Output High Voltage Logical 0 Input Current Logical Transition Current Input Leakage Current Reset Pull-down Resistance Pin Capacitance Power Supply Current Valid port 0,1,2,3,4,5 RES, XTAL1 port 0,1,2,3,4,5 RES, XTAL1 port 0, ALE port 1,2,3,4,5 port 0 port 1,2,3,4,5,ALE port 1,2,3,4,5 port 1,2,3,4,5 port 0 RES Vdd 50 Min. -0.5 0 2.0 70%Vdd Max. 0.8 0.8 Vdd+0.5 Vdd+0.5 0.45 0.45 Unit V V V V V V V V V V uA uA uA Kohm pF mA mA uA Freq=1MHz, Ta=25 Active mode, 16MHz Idle mode, 16MHz Power down mode Test Conditions Vdd=5.0V
2.4 90%Vdd 2.4 90%Vdd -75 -650 10 300 10 25 20 30
IOL=3.2mA IOL=1.6mA IOH=-800uA IOH=-80uA IOH=-60uA IOH=-10uA Vin=0.45V Vin=2.0V 0.45VNote1: Under steady state (non-transient) conditions, IOL must be externally Limited as follows: Maximum IOL per port pin: 10mA Maximum IOL per 8-bit port: port 0 : 26mA port 1,2,3,4,5 : 15mA Maximum total IOL for all output pins : 71mA If IOL exceeds the condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. Icc Active Mode Test Circuit
VDD
Icc
P0
NC Clock Signal
XTAL2 XTAL1 VSS
SM59R16A2
RESET
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 65 Ver.B SM59R16A2/SM59R08A2 06/2009
SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded
Application Reference
Valid for SM59R16A2/SM59R08A2 X'tal C1 C2 X'tal C1 C2 2MHz 47 pF 47 pF 16MHz 30 pF 30 pF 6MHz 35 pF 35 pF 25MHz 25 pF 25 pF 10MHz 30 pF 30 pF 12MHz 30 pF 30 pF
XTAL2
Crystal
C2 C1
SM59R16A2 (SM59R08A2)
XTAL1 VSS
NOTE: Oscillation circuit may differ with different crystal or ceramic resonator in higher oscillation frequency which was due to each crystal or ceramic resonator has its own characteristics. User should check with the crystal or ceramic resonator manufacture for appropriate value of external components. Please see SM59R16A2/SM59R08A2 application note for details.
Reset Pin and 3.3V Regulator (VDD = 5V or 3.3V)
5V 10uF
RESET VDD3V
0.1uF
VDD
4.7uF 5V
3.3V 10uF
RESET
VDD3V
3.3V 0.1uF 4.7uF
6.8K
6.8K
VDD
SM59R16A2
5V 0.1uF
AVDD VDDIO AVDD3V
0.1uF
SM59R16A2
3.3V
VDDIO AVDD3V
3.3V 0.1uF 4.7uF
0.1uF 4.7uF 5V 0.1uF
VSSIO VSS AVSS
0.1uF
AVDD
VSSIO
VSS
AVSS
Timing Critical, Requirement of External Clock
(Vss=0.0V is assumed)
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 66 Ver.B SM59R16A2/SM59R08A2 06/2009
SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded MCU writer list
Company Advantech 7F, No.98, Ming-Chung Rd., Shin-Tien City, Taipei, Taiwan, ROC Web site: http://www.aec.com.tw Contact info Tel:02-22182325 Fax:02-22182435 E-mail: aecwebmaster@advantech.com.tw Programmer Model Number Lab Tool - 48XP/UXP Lab Tool - 848/848XP
Hi-Lo 4F.,No.18,Lane 79,Rueiguang Rd.,Neihu,Taipei,Taiwan R.O.C. Web site: http://www.hilosystems.com.tw
Tel: 02-87923301 Fax:02-87923285 E-mail: support@hilosystems.com.tw
All - 100 series
Leap 6th F1-4, Lane 609, Chunghsin Rd., Sec. 5, Sanchung, Taipei , Taiwan, ROC Web site: http://www.leap.com.tw Xeltek Electronic Co., Ltd Bldg 6-31 Meizhiguo garden, #2 Jiangjun Ave., Jiangning, Nanjing, China 211100 Web site: http://www.xeltek-cn.com Guangzhou Zhiyuan Electronic Co.,Ltd Floor 2,No.7 building,Huangzhou Industrial Estate,Chebei Road,Tianhe district,Guangzhou,China 510660 Web site: http://www.embedtools.com/ TianJin Weilei technology ltd Rm 357,Venturetech Center,12 Keyan West Road Nankai District,Tianjin,P.R.C, 300192 Web site: http://www.weilei.com.cn/
Tel: 886-2-29991860 Fax:02-29990015 E-mail: service@leap.com.tw
Leap-48
Tel: + 86-25-52765201, E-mail: f_l@xeltek.com.cn zxl@xeltek.com.cn
Superpro 280U Superpro 580U Superpro 3000U Superpro 9000U
TEL: +86-20-28872449 E-mail: mcu@programtec.com
SmartPRO 5000U/X8
TEL: + 86-22-87891218#801 E-mail: weilong@weilei.com.cn cm@weilei.com.cn
VP-890;VP-980;VP-880;VP-680 VP-480;VP-380;VP-280;VP-190
Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 67 Ver.B SM59R16A2/SM59R08A2 06/2009

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